diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef901c3f448879037c51ea5357302b4c71fbbef..e6d4a20438549976738091ce1d906feb71e7f960 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -7,6 +7,7 @@ config SYS_ARCH
config ARM64
bool
select PHYS_64BIT
+ select SYS_CACHE_SHIFT_6
config DMA_ADDR_T_64BIT
bool
@@ -20,37 +21,47 @@ config HAS_THUMB2
config CPU_ARM720T
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM920T
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM926EJS
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM946ES
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM1136
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM1176
bool
select HAS_VBAR
+ select SYS_CACHE_SHIFT_5
config CPU_V7
bool
select HAS_VBAR
select HAS_THUMB2
+ select SYS_CACHE_SHIFT_6
config CPU_V7M
bool
select HAS_THUMB2
+ select SYS_CACHE_SHIFT_5
config CPU_PXA
bool
+ select SYS_CACHE_SHIFT_5
config CPU_SA1100
bool
+ select SYS_CACHE_SHIFT_5
config SYS_CPU
default "arm720t" if CPU_ARM720T
@@ -79,6 +90,21 @@ config SYS_ARM_ARCH
default 4 if CPU_SA1100
default 8 if ARM64
+config SYS_CACHE_SHIFT_5
+ bool
+
+config SYS_CACHE_SHIFT_6
+ bool
+
+config SYS_CACHE_SHIFT_7
+ bool
+
+config SYS_CACHELINE_SIZE
+ int
+ default 128 if SYS_CACHE_SHIFT_7
+ default 64 if SYS_CACHE_SHIFT_6
+ default 32 if SYS_CACHE_SHIFT_5
+
config SEMIHOSTING
bool "support boot from semihosting"
help
@@ -867,6 +893,7 @@ config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
select OF_CONTROL
+ select SYS_CACHE_SHIFT_7
endchoice
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 7244c2e7d79e6e6dd34b3009d10b4dc10db4b07b..ef32c3f0abd4e92b0950f65ca986dd9cf5f06c39 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -53,11 +53,6 @@ static void cache_flush(void)
}
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 2119382ab2451583a0399672e0bf914389d8743c..02cb24c24ffb0c08b063f8a59f1181c57331e18e 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -8,11 +8,6 @@
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
index 7aba112c714b61a7d40d2c0f5703f0fac990eace..d26354e1aadcbc35ad95c712dc47a7314c4d8d0d 100644
--- a/arch/arm/cpu/pxa/cache.c
+++ b/arch/arm/cpu/pxa/cache.c
@@ -8,11 +8,6 @@
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
index e062da18b113b0eff0550881f583da2e843a66f4..6ebc759f4b9675c80c68d385e2698b03998dede5 100644
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -16,8 +16,6 @@
#define _ARMD1_CONFIG_H
#include <asm/arch/armada100.h>
-/* default Dcache Line length for armada100 */
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b0ad4b462689f6e48ab89d6f2ad3cb2069244002..527998111f318509e44909a83506c2a146deb8e5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -36,7 +36,6 @@
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 64
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
@@ -150,7 +149,6 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index d408fe40561a51523b85eda7986c061475685d38..56d8f3247f54a16707a591583e8d7e645c7aeabf 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -7,8 +7,6 @@
#ifndef _ASM_ARMV7_LS102XA_CONFIG_
#define _ASM_ARMV7_LS102XA_CONFIG_
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define OCRAM_BASE_ADDR 0x10000000
#define OCRAM_SIZE 0x00010000
#define OCRAM_BASE_S_ADDR 0x10010000
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index e73cc0765326911f634a192dc251f29cc2abd7b8..3e79fa3224ec2b2810325f51b12877c1c2536e48 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -9,8 +9,6 @@
#define ARCH_MXC
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_SOC_BASE_ADDR 0x40000000
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index ac37e4f8e689d37b2748bc580df15fa77db240dd..53bf05439d91c20188ee5de24c89e5d6ddedc16f 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -9,12 +9,6 @@
#define ARCH_MXC
-#ifdef CONFIG_MX6UL
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#else
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 74917f0e69d8bf3c30ec1fa962396ef872294e69..d33be313c6ee22876b4216ceca2ab42af706a6d0 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -9,8 +9,6 @@
#define ARCH_MXC
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define ROM_SW_INFO_ADDR 0x000001E8
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x00017FFF
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 16e65c36a9a5dacefadd4281b30a8a4d4bc77c41..5400cbe18ff435cf207fd46e2ea0e8d819105560 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -43,14 +43,11 @@ void dram_bank_mmu_setup(int bank);
#endif
/*
- * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
- * use that value for aligning DMA buffers unless the board config has specified
- * an alternate cache line size.
+ * The value of the largest data cache relevant to DMA operations shall be set
+ * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger
+ * value than found in the L1 cache but this is OK to use in terms of
+ * alignment.
*/
-#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 64
-#endif
#endif /* _ASM_CACHE_H */
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index d330b09434a46df1ab6505bf8b46c54e90ccfa21..4f72f8914cc7bc5e18220de629704fbe8176dced 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -10,10 +10,6 @@
#include <common.h>
#include <malloc.h>
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
/*
* Flush range from all levels of d-cache/unified-cache.
* Affects the range [start, start + size - 1].
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index 60b60aa6f6e614c000c87751fae014cfcb296145..446457fd812f0a1867e81c3cba8cc04b4559edb2 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -24,8 +24,6 @@
#endif /* CONFIG_KW88F6281 */
#include <asm/arch/soc.h>
-#define CONFIG_SYS_CACHELINE_SIZE 32
- /* default Dcache Line length for kirkwood */
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index 4df70d7d3f06ab17e79fca20483840bc8586ef83..1b35e0802b240c19509dc2ae956049b1f228ae48 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -26,8 +26,6 @@
#define MV88F78X60 /* for the DDR training bin_hdr code */
#endif
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_L2_PL310
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index a8a0b90c39b289f6ead2b7b5601d41716f16eaf2..89614581bb1ff6329f038d40a3420aaaa616a9d6 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -75,6 +75,7 @@ config ARCH_UNIPHIER_LD6B
config CACHE_UNIPHIER
bool "Enable the UniPhier L2 cache controller"
depends on ARCH_UNIPHIER_32BIT
+ select SYS_CACHE_SHIFT_7
default y
help
This option allows to use the UniPhier System Cache as L2 cache.
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index a65d1a884b0150c6b6bc3fec43c630985a7e56c5..30c42781cafb815537180d745ddbfcf40b349a3d 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -13,8 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 4d88aac63750d1e86188aaf7b92699e8bf450951..ef4a8baf43ce88ea39ada6a3504899e0f2515ffa 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -18,8 +18,6 @@
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 0467953566c65062da070d7a175dd48d15e6fa4f..518b904807bee8725f90f76592dc01c0593baecf 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -11,7 +11,6 @@
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
@@ -49,7 +48,6 @@
/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Since SPL did pll and ddr initialization for us,
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 9257c5f029230cee80e184b2a3b9aab0066e3bcd..051186d4bbb4e361c5fed438d29ee2ee21ceb970 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -12,8 +12,6 @@
#include <asm/hardware.h>
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
index 770dd872f977c6e406736726bb2bd4965e7d9703..b9688014cd2e5072dca94c5fdd6095a66b5edcb6 100644
--- a/include/configs/bcm23550_w1d.h
+++ b/include/configs/bcm23550_w1d.h
@@ -127,7 +127,6 @@
/* Commands */
#define CONFIG_FAT_WRITE
-#define CONFIG_SYS_CACHELINE_SIZE 64
#undef CONFIG_USB_GADGET_VBUS_DRAW
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USBID_ADDR 0x34052c46
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index df0b2bac39d87aba2d25b69982d1e7e62cc580c8..f38f08135569583a6113286da155ca9cd5e74856 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -126,7 +126,6 @@
/* Commands */
#define CONFIG_FAT_WRITE
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_USBID_ADDR 0x34052c46
#endif /* __BCM28155_AP_H */
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index 50cd7430b59b915d14a4d4a09eda553b2b44c8a0..b5e502921783cbfe7779bdf3d44632b97c3f53c2 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -11,8 +11,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* Memory configuration
* (these must be defined elsewhere)
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index a94b1e27115574d99c875b885b0b958b528b4923..04da877db5f70db8fa3efa9204e6909d821a7c12 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -15,7 +15,6 @@
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index ea9983bc7d436335c1a8fcda6ecb1892136efd9d..a89ccb73b178b92b93b4590122c871e6655ddf5b 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -10,8 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
*/
@@ -30,7 +28,6 @@
* Although the default iss 64, we still define it
* to be on the safe side once the default is changed.
*/
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 5d94f133cba90838626e174c521215b2e1af2862..b896d4d79a4a221fe74c58a00c464c69b017e5d0 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -79,7 +79,6 @@
/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Since SPL did pll and ddr initialization for us,
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 58925952dddfba956b4bf0b47e82f9ba1194486d..fb68e598b2333b1a23cf9616b2fb98454638a1cb 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -12,8 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
@@ -207,8 +205,6 @@
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
/* USB Host Support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_VF
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 28ea15b596ac328e2ea6cb50e8028f5ea534b47f..746475d45fecb4afa7b747783ff4e7b90db5b1e3 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -118,7 +118,6 @@
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
/* bootstrap + u-boot + env in nandflash */
diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index 1dbe2194f86c55ef52ae9f5f8a754a712fda7c08..cc7ab8365d1ea72579d4ba45e13c21bd9511409b 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -27,8 +27,6 @@
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* UART */
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index fbe0fa969d6e3335a3805dd02f9d19ea533a5509..fdbaf027ac474b43465549be69bd899602da528d 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -15,7 +15,6 @@
#define CONFIG_BOARD_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_REVISION_TAG
/* SD/MMC configuration */
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index f2ed7982b4531f6a0abf877f5b61028dc18f65b4..153878732b8e9ca83ec5fb210b6de690c441a20c 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -13,7 +13,6 @@
#include "exynos-common.h"
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EXYNOS_SPL
#ifdef FTRACE
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 824aca45b647d7331643d49cf13e3f71ec2247ea..e84803dfb2b64b70c298da985df742b51c9e3cd0 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -19,7 +19,6 @@
#define CONFIG_MX35
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index ffcc4d26307074543e9451560beecfe7db185075..9cbccd9dc9e977e368819f01540377686620eead 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -21,9 +21,6 @@
#define CONFIG_SUPPORT_RAW_INITRD
-/* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_IDENT_STRING "hikey"
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index b08cf2161db7d4648247b6bcc0a779b4852f2b51..8b957996a7b207f1abd292b1f81b6efb08353457 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -24,7 +24,6 @@
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Platform
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 94f351615940583ab07bdcf84adee60e8fcf7d65..a4b296ab8ffa7b1f1540f3f904ecacd1afec31d6 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -10,8 +10,6 @@
#undef DEBUG
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SH73A0
#define CONFIG_KZM_A9_GT
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 0c6e1117d4fda50b38489894efaca7041980d658..8387f1920d3a3822fc39927273da70eca106d496 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -25,8 +25,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h
index eaf6a9c08a4c1ce1dcea12d811e8179218d200cd..3bba2e6658ca4251f31eef052478b2fab9f590aa 100644
--- a/include/configs/meson-gxbb-common.h
+++ b/include/configs/meson-gxbb-common.h
@@ -10,7 +10,6 @@
#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_IS_NOWHERE 1
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index cd154a4bbb3083e57d2a4fdbc719964098e0ad84..cdae54425341b800f6a4add3c7c3b5e30030d6de 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -19,8 +19,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 4dbe2b62d14bd94a375593257c9fa4e40b77e361..fc5de034fe34197ef23a3bfe263e8e922b0a100b 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -275,8 +275,6 @@
#define CONFIG_OMAP3_SPI
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Defines for SPL */
#define CONFIG_SPL_OMAP3_ID_NAND
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 82e0d5000ca93bd7d5c5cde61cd877699979de90..4310bada485a32d5a9f95795222840b3eb597a42 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -192,8 +192,6 @@
#define CONFIG_OMAP3_SPI
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Defines for SPL */
#define CONFIG_SPL_OMAP3_ID_NAND
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 52a24d37b882b31108ac24049cbf7ffa246f91ff..e87b4c0118b747c01f093a0ef27912e6f5ad6953 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -340,8 +340,6 @@
/* Uncomment to define the board revision statically */
/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200800
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 49a8b3f5ef43435bb9b59e248258ce0079bedeea..05a43610e524c258e74467c0dd30c18b773903a9 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -82,7 +82,6 @@
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
-#define CONFIG_SYS_CACHELINE_SIZE 64
/* TWL4030 */
#define CONFIG_TWL4030_PWM
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index fbd0c2a07085dd3a1d9b8e49aef3f00e519ec698..618a546dedbee09b6ded2ee0d6c04f4168396812 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -215,7 +215,6 @@
/* Initial RAM setup */
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_CACHELINE_SIZE 64
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 380ec129cda2fa1033ac6dd179cb66c7fc333261..9e7bd88adb000a8c745c7ff104178661d8eabbae 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -119,6 +119,4 @@
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 99d9fc3b256904dfdf2620711fde9f9b1e11fc1b..6397051948133e3ebb4053b573c3b8cfc66d6e9e 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -176,8 +176,6 @@
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#ifdef CONFIG_CMD_NET
/* Ethernet (LAN9211 from SMSC9118 family) */
#define CONFIG_SMC911X
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 74e22db15121d22879a64012ebb6c53fe643f78e..57a76306e24842991125f481d7966fc085670c40 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 80313fc8c57120f29f46b1f5477fd92a4696a060..8f91e8e001294c02ff29b1e116295bcf6c92ff57 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -9,8 +9,6 @@
#ifndef __RCAR_GEN2_COMMON_H
#define __RCAR_GEN2_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_DFL
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 21d468354beca5ed3f3b99e82173a0aa98bd2f3a..101a3ed5bd73b5765c411e3674abe427f6d4f708 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -6,8 +6,6 @@
#ifndef __CONFIG_RK3036_COMMON_H
#define __CONFIG_RK3036_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch/hardware.h>
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index d3d4c680e99c207c092dcb57a4f145aeb4a5e035..601186c5c1e923448820ed7b6a15dd0f4f5a91f2 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_RK3288_COMMON_H
#define __CONFIG_RK3288_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch/hardware.h>
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 6875308e11b22a110bdae8d4bff318b01906537c..e9626a5e398b050ddc0b05ce1e3d86ddc82c501d 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_RK3399_COMMON_H
#define __CONFIG_RK3399_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_SIZE 0x2000
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index dbbb81efa99f527b2617e0f5c33a2c8ecee5ac38..752cc319fceb3e4e141268ed9927691b32889ef3 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -14,12 +14,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-#ifdef CONFIG_BCM2835
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#else
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#endif
-
/* Architecture, CPU, etc.*/
#define CONFIG_ARCH_CPU_INIT
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 87e51d0aa9a2f9799692be9eabd0f31e7765e875..61c5663c40828d2773e319a80d90f3cb9f5e6dca 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -17,8 +17,6 @@
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
@@ -236,8 +234,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8998
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index eab665c2866b66702593bd0feed04f85cdbe872a..3d25e3db3e6bb37c830a42e25771279821de5c28 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -36,8 +36,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* commands to include */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 076a5ce2992f5b9426db31df176d51154b1fb030..8ad8f24cc91e53f2a6e8b154181ba80312483a18 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -170,8 +170,6 @@
#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-
-#define CONFIG_SYS_CACHELINE_SIZE 0x2000
#endif
/* General Boot Parameter */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 84a188af3a6e7bf07c8d6890d48e7cb15fbea464..9d52689b80fdef41f432dd90f6f56f59af4a3d35 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -12,8 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
* (easy to change)
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index fb348a5cd26e53c14e391c9a41791e87dd4b9cc3..e2f5e60b2aa57be88bf2a5188a1065c19be84a43 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -16,8 +16,6 @@
* CPU
*/
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_ARM_ARCH_CP15_ERRATA
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f654f945bc112b777a8e3a14c72139e2da291285..ce5781b806524f1cd7027cb560c15e14d39b3fff 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -75,7 +75,6 @@
/*
* Cache
*/
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b9aa62b2af684ec0304eb04119a3726fe89fe22e..f64edd4b0fe0aba46bd07e632583c7a0b75c76a3 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -55,7 +55,6 @@
/* CPU */
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 73ff416aed2a2837ac83ea502cf85ed0e9f32b93..521306509599c7bab80502ba2ca799c769aafab6 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -23,8 +23,6 @@
#define CONFIG_SYS_TEXT_BASE 0x80008000
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 6616d7396e74dcc26df9b4c7199a6ddf7471729d..52bd8370a0323cf3e67fbeecfcd2bdfbb3f6b4b4 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -13,8 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 2d091db07d97e974f5d2d082548be71e8392a2aa..513e6552548afd6149a10827dbb5792d9eecc0a9 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -133,8 +133,6 @@
#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-
-#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
#endif
/* SPI EEPROM */
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 21454d47cb5f6935374757a02b6e5f94577c4b76..107a0f8803313fd82d4b120a5ba63d008f01a8d4 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -8,9 +8,6 @@
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* NS16550 Configuration
*/
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index 39e74f023fdad6c0ff1f9a8ba6bf4cfe9daaca37..8cf9bac15680c78c912be71d868eb24227eaf627 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -10,9 +10,6 @@
#include "tegra-common.h"
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* NS16550 Configuration
*/
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
index aa7b9d038a7e3be5bb1531f80477959e9a4fae5a..98e4fc2d252babd82d65230479223cb42353104b 100644
--- a/include/configs/tegra186-common.h
+++ b/include/configs/tegra186-common.h
@@ -9,9 +9,6 @@
#include "tegra-common.h"
-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* NS16550 Configuration
*/
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 00e85c48c41bba41f136dad1f6f0e037a1aaabf5..793310ff473d3d119989688254262711c3667140 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -9,9 +9,6 @@
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
/*
* Errata configuration
*/
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index 8f35a7bf3dc691e432154b9ac6608012a38c0961..874fe34d4f4d1796a434c1a5ed1467202ba10ccf 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -10,9 +10,6 @@
#include "tegra-common.h"
-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* NS16550 Configuration
*/
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 9afd86484bb288140354d7d3f9be5cc0f4cf7088..baf3d00f34ba5272937ac657fed3339506791507 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -9,9 +9,6 @@
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
/*
* Errata configuration
*/
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 3c058832e17658fff660cebfd2305093e74ac8b6..732854eb306e2b0472458a61acbc1f3b72357537 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -16,8 +16,6 @@
#ifndef __CONFIG_TI814X_EVM_H
#define __CONFIG_TI814X_EVM_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_TI81XX
#define CONFIG_TI814X
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 05fd00fd5d270d7a3d904e29262d44262eda2e72..17f12a898a8df79d710fb8e26a460a5878e7d493 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -10,8 +10,6 @@
#ifndef __CONFIG_TI816X_EVM_H
#define __CONFIG_TI816X_EVM_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_TI81XX
#define CONFIG_TI816X
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index bcd56fc08dc13a62d2a744e194fb68acd402b9fd..a9b10d053297580d1cd81523c5564e81790974cc 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -14,7 +14,6 @@
#define CONFIG_AM33XX
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 4aa262e1a8710dec3fb6f9812da431deff5864ab..c830c0c0bf6863afc76ab8fa8c362dcb7b52091f 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -200,7 +200,6 @@
#define CONFIG_USB_STORAGE
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_FAT
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 32877d1964ded5db4c4d5af15bb9ccd36573cced..c54b7b55c4f49d1fa356d74b7c65c96acff6f60e 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -18,8 +18,6 @@
* High Level Configuration Options
*/
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 5fad3c1242c5b1d371c9f2b844888d52d9326aaf..e6e88c528252e1360ec8e937a04c9acc13c85f7f 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -26,7 +26,6 @@
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
#endif
-#define CONFIG_SYS_CACHELINE_SIZE 32
/* Get CPU defs */
#include <asm/arch/cpu.h>
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 3589cdc3a88e8830e4b547240ae393f098308721..e42c88e3b92817d15138253b8cb3986ace683e78 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -23,8 +23,6 @@
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_798870
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT2_BASE
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 127a9689482fc0a8a15c7620d3f1d311dee22206..ae0e89c59456f0e42eeda990de76590a4b92d97c 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -16,8 +16,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* High Level Configuration Options */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_OMAP /* in a TI OMAP core */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 0f5b20ff48c4ec4dd28fb32a2b5b670b08ad33d3..f41a0b1cad6a9d1e414b1cfeee393e38e7691b64 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -30,12 +30,6 @@
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */
-#ifdef CONFIG_CACHE_UNIPHIER
-#define CONFIG_SYS_CACHELINE_SIZE 128
-#else
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 9aca3936fb1329cd68b875f5ea90977448dd42d0..71c4a1f08d62c49d89908714a2cf4c98c8d81849 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -19,9 +19,6 @@
#define CONFIG_SUPPORT_RAW_INITRD
-/* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_IDENT_STRING " vexpress_aemv8a"
/* Link Definitions */
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 51898e623cbf19e7605132fb0e0719ed2338f8cd..a8eba314e30de8b5605e7afb81b9ede975771087 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -118,8 +118,6 @@
#define CONFIG_SYS_MEMTEST_START V2M_BASE
#define CONFIG_SYS_MEMTEST_END 0x20000000
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_SYS_L2CACHE_OFF 1
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index c4a1fd091ab671332fc97a9e0587f64a960b075b..33f966ac6e4718e4a5a93191573e86d130b3bbda 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 153466a623ffef1817be49168209899680ca9522..de6b1838d7654e7311626463b307dc88f41ecd43 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -19,7 +19,6 @@
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index ca60e5d3d9cd1155243ccdb747bdcd7264b42d68..02f0e4c9a9a8563e068594fa40fdc56107acc3a8 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -34,9 +34,6 @@
/* Have release address at the end of 256MB for now */
#define CPU_RELEASE_ADDR 0xFFFFFF0
-/* Cache Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#if !defined(CONFIG_IDENT_STRING)
# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
#endif
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index e59e412d58a62ba3c39b97662659da839408ea14..5f7fefde3d5649bf8b32195f5656cd32171ba66c 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -16,8 +16,6 @@
#endif
/* Cache options */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
# define CONFIG_SYS_L2_PL310