diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0e7fde13772288bf12718b8e0acaf581eb9bd95..f5d4d3968383c7df41ad7936e5ad501b7814ce9c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -528,6 +528,12 @@ config ARCH_BCM283X
imply CMD_DM
imply FAT_WRITE
+config ARCH_BCM6858
+ bool "Broadcom BCM6858 family"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
+
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
select CPU_V7A
@@ -1490,6 +1496,7 @@ source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/broadcom/bcm23550_w1d/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
+source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/broadcom/bcmns2/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index c8bebabdf6f44f00258c5da8095d6df16d50d999..ff42791fb440911a1561057824b8cc6d9b1af55e 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -144,6 +144,13 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
A value 0 or no definition of it works for single cluster system.
System with multi-cluster should difine their own exact value.
+config ARMV8_EA_EL3_FIRST
+ bool "External aborts and SError interrupt exception are taken in EL3"
+ default n
+ help
+ Exception handling at all exception levels for External Abort and
+ SError interrupt exception are taken in EL3.
+
if SYS_HAS_ARMV8_SECURE_BASE
config ARMV8_SECURE_BASE
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
index 097f91bace496117302199e4a8f1ae8cec27ffdd..358df8fee9c32a1d5956e5a1252e48b8f88fa896 100644
--- a/arch/arm/cpu/armv8/psci.S
+++ b/arch/arm/cpu/armv8/psci.S
@@ -236,6 +236,28 @@ handle_sync:
b unhandled_exception
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+/*
+ * Override this function if custom error handling is
+ * needed for asynchronous aborts
+ */
+ENTRY(plat_error_handler)
+ ret
+ENDPROC(plat_error_handler)
+.weak plat_error_handler
+
+handle_error:
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ mov x9, #1
+ msr spsel, x9
+ mov sp, x0
+
+ bl plat_error_handler /* Platform specific error handling */
+deadloop:
+ b deadloop /* Never return */
+#endif
+
.align 11
.globl el3_exception_vectors
el3_exception_vectors:
@@ -261,7 +283,11 @@ el3_exception_vectors:
.align 7
b unhandled_exception /* FIQ, Lower EL using AArch64 */
.align 7
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+ b handle_error /* SError, Lower EL using AArch64 */
+#else
b unhandled_exception /* SError, Lower EL using AArch64 */
+#endif
.align 7
b unhandled_exception /* Sync, Lower EL using AArch32 */
.align 7
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1cbb45d679a2d682140e610f6712c8ab8d418b1c..7ed222db8694904a4fa731ffd974fa3861326035 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -559,7 +559,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb
-dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
index 98aadb0f81c5e04153f0ac4ad4f5fdea1bd0bf2f..1d158cfda15f2653fe829aa4faf610f5a926f883 100644
--- a/arch/arm/dts/am3517-evm.dts
+++ b/arch/arm/dts/am3517-evm.dts
@@ -127,6 +127,7 @@
status = "okay";
pinctrl-names = "default";
enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */
+ vcc-supply = <&vdd_io_reg>;
port {
lcd_in: endpoint {
@@ -154,6 +155,7 @@
bl: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
+ power-supply = <&vdd_io_reg>;
pinctrl-0 = <&backlight_pins>;
pwms = <&pwm11 0 5000000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
@@ -168,6 +170,13 @@
ti,timers = <&timer11>;
#pwm-cells = <3>;
};
+
+ /* HS USB Host PHY on PORT 1 */
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
+ #phy-cells = <0>;
+ };
};
&davinci_emac {
@@ -203,6 +212,7 @@
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
+ vcc-supply = <&vdd_io_reg>;
};
};
@@ -220,15 +230,21 @@
cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */
};
-&mmc2 {
+&mmc3 {
status = "disabled";
};
-&mmc3 {
- status = "disabled";
+&usbhshost {
+ port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <&hsusb1_phy>;
};
&omap3_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_rst_pins>;
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
@@ -287,4 +303,32 @@
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
>;
};
+
+ hsusb1_rst_pins: pinmux_hsusb1_rst_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_pins>;
+
+ hsusb1_pins: pinmux_hsusb1_pins {
+ pinctrl-single,pins = <
+ OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
+ OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
+ OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */
+ OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */
+ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */
+ OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */
+ OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */
+ OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */
+ OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */
+ OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */
+ OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */
+ OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
+ >;
+ };
};
diff --git a/arch/arm/dts/am3517-som.dtsi b/arch/arm/dts/am3517-som.dtsi
index a6d5ff73c163074b03f21ea77aed21103f84d096..dae6e458e59fe7e4b49c65c78ed5224169a4407c 100644
--- a/arch/arm/dts/am3517-som.dtsi
+++ b/arch/arm/dts/am3517-som.dtsi
@@ -14,6 +14,32 @@
cpu0-supply = <&vdd_core_reg>;
};
};
+
+ wl12xx_buffer: wl12xx_buf {
+ compatible = "regulator-fixed";
+ regulator-name = "wl1271_buf";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_buffer_pins>;
+ gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
+ regulator-always-on;
+ vin-supply = <&vdd_1v8_reg>;
+ };
+
+ wl12xx_vmmc2: wl12xx_vmmc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_wkup_pins>;
+ gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&wl12xx_buffer>;
+ };
};
&gpmc {
@@ -64,7 +90,6 @@
regulators {
vdd_core_reg: VDCDC1 {
regulator-name = "vdd_core";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@@ -72,7 +97,6 @@
vdd_io_reg: VDCDC2 {
regulator-name = "vdd_io";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -80,7 +104,6 @@
vdd_1v8_reg: VDCDC3 {
regulator-name = "vdd_1v8";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -88,7 +111,6 @@
vdd_usb18_reg: LDO1 {
regulator-name = "vdd_usb18";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -96,7 +118,6 @@
vdd_usb33_reg: LDO2 {
regulator-name = "vdd_usb33";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -126,8 +147,63 @@
};
};
+&mmc2 {
+ interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;
+
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&wl12xx_vmmc2>;
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+
+ bluetooth {
+ compatible = "ti,wl1271-st";
+ enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */
+ max-speed = <3000000>;
+ };
+};
+
&omap3_pmx_core {
+ wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */
+ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */
+ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */
+ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */
+ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */
+ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */
+ OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
+ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
+ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
+ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
+ OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */
+ >;
+ };
+
rtc_pins: pinmux_rtc_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
@@ -139,4 +215,23 @@
OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */
>;
};
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
+ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */
+ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
+ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
+ OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */
+ >;
+ };
+};
+
+&omap3_pmx_wkup {
+
+ wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
+ >;
+ };
};
diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi
index 4b6062b631b1a73813f56e5a447a617a911700a3..23ea381d363fd12e6d9ac7f08e8613f1bf12443e 100644
--- a/arch/arm/dts/am3517.dtsi
+++ b/arch/arm/dts/am3517.dtsi
@@ -91,6 +91,11 @@
};
};
+/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
+&usb_otg_hs {
+ status = "disabled";
+};
+
&iva {
status = "disabled";
};
diff --git a/arch/arm/dts/at91sam9260-smartweb.dts b/arch/arm/dts/at91sam9260-smartweb.dts
index e59781bf45be969279296bb4edd9e0e3aefccb10..a22de2d927db994b1475e94c3b36759a30a7121e 100644
--- a/arch/arm/dts/at91sam9260-smartweb.dts
+++ b/arch/arm/dts/at91sam9260-smartweb.dts
@@ -89,6 +89,7 @@
};
watchdog@fffffd40 {
+ timeout-sec = <15>;
status = "okay";
};
diff --git a/arch/arm/dts/at91sam9g20-taurus.dts b/arch/arm/dts/at91sam9g20-taurus.dts
index 7931c0af7b49c8295aedcf8a95f0bb581af7f6fa..cee228bb8cf5e57c4449f3eb954bfb8cee32003b 100644
--- a/arch/arm/dts/at91sam9g20-taurus.dts
+++ b/arch/arm/dts/at91sam9g20-taurus.dts
@@ -98,6 +98,7 @@
};
watchdog@fffffd40 {
+ timeout-sec = <15>;
status = "okay";
};
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9869d729d348e386764312afa804204c3edf01f3
--- /dev/null
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+ compatible = "brcm,bcm6858";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ next-level-cache = <&l2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ next-level-cache = <&l2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ next-level-cache = <&l2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+
+ uart0: serial@ff800640 {
+ compatible = "brcm,bcm6858-uart";
+ reg = <0x0 0xff800640 0x0 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts
new file mode 100644
index 0000000000000000000000000000000000000000..0c59f94710c97925d9e05b6390c42be3f80d3a5f
--- /dev/null
+++ b/arch/arm/dts/bcm968580xref.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+/dts-v1/;
+
+#include "bcm6858.dtsi"
+
+/ {
+ model = "Broadcom bcm68580xref";
+ compatible = "broadcom,bcm68580xref", "brcm,bcm6858";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 2409344df4fa2f50ee9e91feddc483e0a4a10279..adcd6341e40c02aabef992516a075eb2a14245a8 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -8,13 +8,13 @@
&cbass_main {
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x01800000 0x10000>, /* GICD */
- <0x01880000 0x90000>; /* GICR */
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01880000 0x00 0x90000>; /* GICR */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
@@ -23,9 +23,50 @@
gic_its: gic-its@18200000 {
compatible = "arm,gic-v3-its";
- reg = <0x01820000 0x10000>;
+ reg = <0x00 0x01820000 0x00 0x10000>;
msi-controller;
#msi-cells = <1>;
};
};
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ };
};
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..8c611d16df44bd80ef9ddd0032df241085f8b88f
--- /dev/null
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_mcu {
+ mcu_uart0: serial@40a00000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ };
+};
diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..8d7b47f9dfbf4e43f15b821c92649b594788103a
--- /dev/null
+++ b/arch/arm/dts/k3-am65-wakeup.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_wakeup {
+ dmsc: dmsc {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mbox-names = "rx", "tx";
+
+ mboxes= <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <1>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ wkup_uart0: serial@42300000 {
+ compatible = "ti,am654-uart";
+ reg = <0x42300000 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ };
+};
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index cede1fa0983c9321511649251cff09c1cdaa4e63..3d4bf369d0304a3afb8bcb43e18ca1eeb2648413 100644
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -16,6 +16,14 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ };
+
chosen { };
firmware {
@@ -46,38 +54,38 @@
cbass_main: interconnect@100000 {
compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
- <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
- <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
- <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
- <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
/* MCUSS Range */
- <0x28380000 0x00 0x28380000 0x03880000>,
- <0x40200000 0x00 0x40200000 0x00900100>,
- <0x42040000 0x00 0x42040000 0x03ac2400>,
- <0x45100000 0x00 0x45100000 0x00c24000>,
- <0x46000000 0x00 0x46000000 0x00200000>,
- <0x47000000 0x00 0x47000000 0x00068400>;
+ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
cbass_mcu: interconnect@28380000 {
compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
- <0x40200000 0x40200000 0x00900100>, /* First peripheral window */
- <0x42040000 0x42040000 0x03ac2400>, /* WKUP */
- <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
- <0x46000000 0x46000000 0x00200000>, /* CPSW */
- <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
cbass_wakeup: interconnect@42040000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* WKUP Basic peripherals */
- ranges = <0x42040000 0x42040000 0x03ac2400>;
+ ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
};
};
};
@@ -85,3 +93,5 @@
/* Now include the peripherals for each bus segments */
#include "k3-am65-main.dtsi"
+#include "k3-am65-mcu.dtsi"
+#include "k3-am65-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..e861cb7c676e2857299d7e1622977fb62ef540bd
--- /dev/null
+++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the AM65x_DRA80xM EMIF Tool:
+ * http://www.ti.com/lit/pdf/spracj0
+ * Configuration Parameters
+ * Memory Type: DDR4
+ * Data Rate: 1600
+ * ECC Enabled: No
+ * Data Width: 32
+ */
+#define DDR_PLL_FREQUENCY 400000000
+#define DDRCTL_MSTR 0x41040010
+#define DDRCTL_RFSHCTL0 0x00210070
+#define DDRCTL_ECCCFG0 0x00000000
+#define DDRCTL_RFSHTMG 0x0061008C
+#define DDRCTL_CRCPARCTL0 0x00008000
+#define DDRCTL_CRCPARCTL1 0x1A000000
+#define DDRCTL_CRCPARCTL2 0x0048051E
+#define DDRCTL_INIT0 0x400100C4
+#define DDRCTL_INIT1 0x004F0000
+#define DDRCTL_INIT3 0x02140501
+#define DDRCTL_INIT4 0x00000020
+#define DDRCTL_INIT5 0x00100000
+#define DDRCTL_INIT6 0x00000480
+#define DDRCTL_INIT7 0x000004E8
+#define DDRCTL_DRAMTMG0 0x0C0A1B0D
+#define DDRCTL_DRAMTMG1 0x00030313
+#define DDRCTL_DRAMTMG2 0x0506050A
+#define DDRCTL_DRAMTMG3 0x0000400C
+#define DDRCTL_DRAMTMG4 0x06020206
+#define DDRCTL_DRAMTMG5 0x04040302
+#define DDRCTL_DRAMTMG6 0x00000004
+#define DDRCTL_DRAMTMG7 0x00000404
+#define DDRCTL_DRAMTMG8 0x03030C05
+#define DDRCTL_DRAMTMG9 0x00020208
+#define DDRCTL_DRAMTMG10 0x001C180A
+#define DDRCTL_DRAMTMG11 0x1106010E
+#define DDRCTL_DRAMTMG12 0x00020008
+#define DDRCTL_DRAMTMG13 0x0B100002
+#define DDRCTL_DRAMTMG14 0x00000000
+#define DDRCTL_DRAMTMG15 0x0000003F
+#define DDRCTL_DRAMTMG17 0x00500028
+#define DDRCTL_ZQCTL0 0x21000040
+#define DDRCTL_ZQCTL1 0x0202FAF0
+#define DDRCTL_DFITMG0 0x04888206
+#define DDRCTL_DFITMG1 0x000A0606
+#define DDRCTL_DFITMG2 0x00000604
+#define DDRCTL_DFIMISC 0x00000001
+#define DDRCTL_ADDRMAP0 0x001F1F1F
+#define DDRCTL_ADDRMAP1 0x003F0808
+#define DDRCTL_ADDRMAP2 0x00000000
+#define DDRCTL_ADDRMAP3 0x00000000
+#define DDRCTL_ADDRMAP4 0x00001F1F
+#define DDRCTL_ADDRMAP5 0x08080808
+#define DDRCTL_ADDRMAP6 0x08080808
+#define DDRCTL_ADDRMAP7 0x00000F0F
+#define DDRCTL_ADDRMAP8 0x00000A0A
+#define DDRCTL_ADDRMAP9 0x00000000
+#define DDRCTL_ADDRMAP10 0x00000000
+#define DDRCTL_ADDRMAP11 0x001F1F00
+#define DDRCTL_DQMAP0 0x00000000
+#define DDRCTL_DQMAP1 0x00000000
+#define DDRCTL_DQMAP4 0x00000000
+#define DDRCTL_DQMAP5 0x00000000
+#define DDRCTL_PWRCTL 0x00000000
+#define DDRCTL_RANKCTL 0x00000000
+#define DDRCTL_ODTCFG 0x0600060C
+#define DDRCTL_ODTMAP 0x00000001
+#define DDRPHY_PGCR0 0x07001E00
+#define DDRPHY_PGCR1 0x020046C0
+#define DDRPHY_PGCR2 0x00F0BFE0
+#define DDRPHY_PGCR3 0x55AA0080
+#define DDRPHY_PGCR6 0x00013001
+#define DDRPHY_PTR2 0x00083DEF
+#define DDRPHY_PTR3 0x00061A80
+#define DDRPHY_PTR4 0x00000120
+#define DDRPHY_PTR5 0x00027100
+#define DDRPHY_PTR6 0x04000320
+#define DDRPHY_PLLCR0 0x021c4000
+#define DDRPHY_DXCCR 0x00000038
+#define DDRPHY_DSGCR 0x02A0C129
+#define DDRPHY_DCR 0x0000040C
+#define DDRPHY_DTPR0 0x041A0B06
+#define DDRPHY_DTPR1 0x28140000
+#define DDRPHY_DTPR2 0x0034E300
+#define DDRPHY_DTPR3 0x02800800
+#define DDRPHY_DTPR4 0x31180805
+#define DDRPHY_DTPR5 0x00250B06
+#define DDRPHY_DTPR6 0x00000505
+#define DDRPHY_ZQCR 0x008A2A58
+#define DDRPHY_ZQ0PR0 0x000077DD
+#define DDRPHY_ZQ1PR0 0x000077DD
+#define DDRPHY_MR0 0x00000214
+#define DDRPHY_MR1 0x00000501
+#define DDRPHY_MR2 0x00000000
+#define DDRPHY_MR3 0x00000020
+#define DDRPHY_MR4 0x00000000
+#define DDRPHY_MR5 0x00000480
+#define DDRPHY_MR6 0x000004E8
+#define DDRPHY_MR11 0x00000000
+#define DDRPHY_MR12 0x00000000
+#define DDRPHY_MR13 0x00000000
+#define DDRPHY_MR14 0x00000000
+#define DDRPHY_MR22 0x00000000
+#define DDRPHY_VTCR0 0xF3C32028
+#define DDRPHY_DX8SL0PLLCR0 0x021c4000
+#define DDRPHY_DX8SL1PLLCR0 0x021c4000
+#define DDRPHY_DX8SL2PLLCR0 0x021c4000
+#define DDRPHY_DTCR0 0x8000B1C7
+#define DDRPHY_DTCR1 0x00010236
+#define DDRPHY_ACIOCR5 0x04800000
+#define DDRPHY_IOVCR0 0x0F0C0C0C
+#define DDRPHY_DX0GCR0 0x00000000
+#define DDRPHY_DX0GCR1 0x00000000
+#define DDRPHY_DX0GCR2 0x00000000
+#define DDRPHY_DX0GCR3 0x00000000
+#define DDRPHY_DX1GCR0 0x00000000
+#define DDRPHY_DX1GCR1 0x00000000
+#define DDRPHY_DX1GCR2 0x00000000
+#define DDRPHY_DX1GCR3 0x00000000
+#define DDRPHY_DX2GCR0 0x40700204
+#define DDRPHY_DX2GCR1 0x00007FFF
+#define DDRPHY_DX2GCR2 0x00000000
+#define DDRPHY_DX2GCR3 0xFFC0010B
+#define DDRPHY_DX3GCR0 0x40700204
+#define DDRPHY_DX3GCR1 0x00007FFF
+#define DDRPHY_DX3GCR2 0x00000000
+#define DDRPHY_DX3GCR3 0xFFC0010B
+#define DDRPHY_DX4GCR0 0x40703220
+#define DDRPHY_DX4GCR1 0x55556000
+#define DDRPHY_DX4GCR2 0xAAAA0000
+#define DDRPHY_DX4GCR3 0xFFE18587
+#define DDRPHY_DX0GCR4 0x0E00B03C
+#define DDRPHY_DX1GCR4 0x0E00B03C
+#define DDRPHY_DX2GCR4 0x0E00B03C
+#define DDRPHY_DX3GCR4 0x0E00B03C
+#define DDRPHY_DX4GCR4 0x0E00B03C
+#define DDRPHY_PGCR5 0x01010004
+#define DDRPHY_DX0GCR5 0x00000049
+#define DDRPHY_DX1GCR5 0x00000049
+#define DDRPHY_DX2GCR5 0x00000049
+#define DDRPHY_DX3GCR5 0x00000049
+#define DDRPHY_DX4GCR5 0x00000049
+#define DDRPHY_DX0GTR0 0x00020002
+#define DDRPHY_DX1GTR0 0x00020002
+#define DDRPHY_DX2GTR0 0x00020002
+#define DDRPHY_DX3GTR0 0x00020002
+#define DDRPHY_DX4GTR0 0x00020002
+#define DDRPHY_ODTCR 0x00010000
+#define DDRPHY_DX8SL0IOCR 0x04800000
+#define DDRPHY_DX8SL1IOCR 0x04800000
+#define DDRPHY_DX8SL2IOCR 0x04800000
+#define DDRPHY_DX8SL0DXCTL2 0x00141830
+#define DDRPHY_DX8SL1DXCTL2 0x00141830
+#define DDRPHY_DX8SL2DXCTL2 0x00141830
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index d4ecb3be1098664fcc646469a1bd40eb03657a1f..143eb6d63092bb9c7e1f2a3dde85b0d165abe543 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -17,56 +17,10 @@
&cbass_main{
u-boot,dm-spl;
- secure_proxy: secure_proxy@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x32c00000 0x100000>,
- <0x32400000 0x100000>,
- <0x32800000 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- dmsc: dmsc {
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- /*
- * In case of rare platforms that does not use am6 as
- * system master, use /delete-property/
- */
- ti,system-reboot-controller;
- mbox-names = "rx", "tx";
-
- mboxes= <&secure_proxy 11>,
- <&secure_proxy 13>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
- };
-
- k3_clks: clocks {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
-
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- };
- };
main_pmx0: pinmux@11c000 {
compatible = "pinctrl-single";
- reg = <0x11c000 0x2e4>;
+ reg = <0x0 0x11c000 0x0 0x2e4>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
@@ -74,28 +28,16 @@
main_pmx1: pinmux@11c2e8 {
compatible = "pinctrl-single";
- reg = <0x11c2e8 0x24>;
+ reg = <0x0 0x11c2e8 0x0 0x24>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
- main_uart0: serial@2800000 {
- compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a";
- reg = <0x02800000 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- status = "disabled";
- u-boot,dm-pre-reloc;
- };
-
sdhci0: sdhci@04F80000 {
compatible = "arasan,sdhci-5.1";
- reg = <0x4F80000 0x1000>,
- <0x4F90000 0x400>;
+ reg = <0x0 0x4F80000 0x0 0x1000>,
+ <0x0 0x4F90000 0x0 0x400>;
clocks = <&k3_clks 47 1>;
power-domains = <&k3_pds 47>;
max-frequency = <25000000>;
@@ -103,8 +45,8 @@
sdhci1: sdhci@04FA0000 {
compatible = "arasan,sdhci-5.1";
- reg = <0x4FA0000 0x1000>,
- <0x4FB0000 0x400>;
+ reg = <0x0 0x4FA0000 0x0 0x1000>,
+ <0x0 0x4FB0000 0x0 0x400>;
clocks = <&k3_clks 48 1>;
power-domains = <&k3_pds 48>;
max-frequency = <25000000>;
@@ -112,12 +54,31 @@
};
-&secure_proxy {
+&cbass_mcu {
+ u-boot,dm-spl;
+ wkup_pmx0: pinmux@4301c000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x4301c000 0x0 0x118>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+};
+
+&cbass_wakeup {
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
};
&k3_pds {
@@ -141,6 +102,7 @@
AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */
AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */
>;
+ u-boot,dm-spl;
};
main_mmc0_pins_default: main_mmc0_pins_default {
@@ -157,6 +119,7 @@
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */
>;
+ u-boot,dm-spl;
};
main_mmc1_pins_default: main_mmc1_pins_default {
@@ -170,6 +133,7 @@
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */
AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */
>;
+ u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..964eb173eb3c64cb655a74fa24842180669541a6
--- /dev/null
+++ b/arch/arm/dts/k3-am654-ddr.dtsi
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/ {
+ memorycontroller: memorycontroller@0298e000 {
+ compatible = "ti,am654-ddrss";
+ reg = <0x0 0x0298e000 0x0 0x200>,
+ <0x0 0x02980000 0x0 0x4000>,
+ <0x0 0x02988000 0x0 0x2000>;
+ reg-names = "ss", "ctl", "phy";
+ clocks = <&k3_clks 20 0>;
+ power-domains = <&k3_pds 20>,
+ <&k3_pds 244>;
+ assigned-clocks = <&k3_clks 20 1>;
+ assigned-clock-rates = <DDR_PLL_FREQUENCY>;
+ u-boot,dm-spl;
+
+ ti,ctl-reg = <
+ DDRCTL_DFIMISC
+ DDRCTL_DFITMG0
+ DDRCTL_DFITMG1
+ DDRCTL_DFITMG2
+ DDRCTL_INIT0
+ DDRCTL_INIT1
+ DDRCTL_INIT3
+ DDRCTL_INIT4
+ DDRCTL_INIT5
+ DDRCTL_INIT6
+ DDRCTL_INIT7
+ DDRCTL_MSTR
+ DDRCTL_ODTCFG
+ DDRCTL_ODTMAP
+ DDRCTL_RANKCTL
+ DDRCTL_RFSHCTL0
+ DDRCTL_RFSHTMG
+ DDRCTL_ZQCTL0
+ DDRCTL_ZQCTL1
+ >;
+
+ ti,ctl-crc = <
+ DDRCTL_CRCPARCTL0
+ DDRCTL_CRCPARCTL1
+ DDRCTL_CRCPARCTL2
+ >;
+
+ ti,ctl-ecc = <
+ DDRCTL_ECCCFG0
+ >;
+
+ ti,ctl-map = <
+ DDRCTL_ADDRMAP0
+ DDRCTL_ADDRMAP1
+ DDRCTL_ADDRMAP2
+ DDRCTL_ADDRMAP3
+ DDRCTL_ADDRMAP4
+ DDRCTL_ADDRMAP5
+ DDRCTL_ADDRMAP6
+ DDRCTL_ADDRMAP7
+ DDRCTL_ADDRMAP8
+ DDRCTL_ADDRMAP9
+ DDRCTL_ADDRMAP10
+ DDRCTL_ADDRMAP11
+ DDRCTL_DQMAP0
+ DDRCTL_DQMAP1
+ DDRCTL_DQMAP4
+ DDRCTL_DQMAP5
+ >;
+
+ ti,ctl-pwr = <
+ DDRCTL_PWRCTL
+ >;
+
+ ti,ctl-timing = <
+ DDRCTL_DRAMTMG0
+ DDRCTL_DRAMTMG1
+ DDRCTL_DRAMTMG2
+ DDRCTL_DRAMTMG3
+ DDRCTL_DRAMTMG4
+ DDRCTL_DRAMTMG5
+ DDRCTL_DRAMTMG6
+ DDRCTL_DRAMTMG7
+ DDRCTL_DRAMTMG8
+ DDRCTL_DRAMTMG9
+ DDRCTL_DRAMTMG11
+ DDRCTL_DRAMTMG12
+ DDRCTL_DRAMTMG13
+ DDRCTL_DRAMTMG14
+ DDRCTL_DRAMTMG15
+ DDRCTL_DRAMTMG17
+ >;
+
+ ti,phy-cfg = <
+ DDRPHY_DCR
+ DDRPHY_DSGCR
+ DDRPHY_DX0GCR0
+ DDRPHY_DX0GCR1
+ DDRPHY_DX0GCR2
+ DDRPHY_DX0GCR3
+ DDRPHY_DX0GCR4
+ DDRPHY_DX0GCR5
+ DDRPHY_DX0GTR0
+ DDRPHY_DX1GCR0
+ DDRPHY_DX1GCR1
+ DDRPHY_DX1GCR2
+ DDRPHY_DX1GCR3
+ DDRPHY_DX1GCR4
+ DDRPHY_DX1GCR5
+ DDRPHY_DX1GTR0
+ DDRPHY_DX2GCR0
+ DDRPHY_DX2GCR1
+ DDRPHY_DX2GCR2
+ DDRPHY_DX2GCR3
+ DDRPHY_DX2GCR4
+ DDRPHY_DX2GCR5
+ DDRPHY_DX2GTR0
+ DDRPHY_DX3GCR0
+ DDRPHY_DX3GCR1
+ DDRPHY_DX3GCR2
+ DDRPHY_DX3GCR3
+ DDRPHY_DX3GCR4
+ DDRPHY_DX3GCR5
+ DDRPHY_DX3GTR0
+ DDRPHY_DX4GCR0
+ DDRPHY_DX4GCR1
+ DDRPHY_DX4GCR2
+ DDRPHY_DX4GCR3
+ DDRPHY_DX4GCR4
+ DDRPHY_DX4GCR5
+ DDRPHY_DX4GTR0
+ DDRPHY_DX8SL0DXCTL2
+ DDRPHY_DX8SL0IOCR
+ DDRPHY_DX8SL0PLLCR0
+ DDRPHY_DX8SL1DXCTL2
+ DDRPHY_DX8SL1IOCR
+ DDRPHY_DX8SL1PLLCR0
+ DDRPHY_DX8SL2DXCTL2
+ DDRPHY_DX8SL2IOCR
+ DDRPHY_DX8SL2PLLCR0
+ DDRPHY_DXCCR
+ DDRPHY_ODTCR
+ DDRPHY_PGCR0
+ DDRPHY_PGCR1
+ DDRPHY_PGCR2
+ DDRPHY_PGCR3
+ DDRPHY_PGCR5
+ DDRPHY_PGCR6
+ >;
+
+ ti,phy-ctl = <
+ DDRPHY_DTCR0
+ DDRPHY_DTCR1
+ DDRPHY_MR0
+ DDRPHY_MR1
+ DDRPHY_MR2
+ DDRPHY_MR3
+ DDRPHY_MR4
+ DDRPHY_MR5
+ DDRPHY_MR6
+ DDRPHY_MR11
+ DDRPHY_MR12
+ DDRPHY_MR13
+ DDRPHY_MR14
+ DDRPHY_MR22
+ DDRPHY_PLLCR0
+ DDRPHY_VTCR0
+ >;
+
+ ti,phy-ioctl = <
+ DDRPHY_ACIOCR5
+ DDRPHY_IOVCR0
+ >;
+
+ ti,phy-timing = <
+ DDRPHY_DTPR0
+ DDRPHY_DTPR1
+ DDRPHY_DTPR2
+ DDRPHY_DTPR3
+ DDRPHY_DTPR4
+ DDRPHY_DTPR5
+ DDRPHY_DTPR6
+ DDRPHY_PTR2
+ DDRPHY_PTR3
+ DDRPHY_PTR4
+ DDRPHY_PTR5
+ DDRPHY_PTR6
+ >;
+
+ ti,phy-zq = <
+ DDRPHY_ZQ0PR0
+ DDRPHY_ZQ1PR0
+ DDRPHY_ZQCR
+ >;
+ };
+};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
new file mode 100644
index 0000000000000000000000000000000000000000..081a2eceb291e3479293079b21a17c4058ca4198
--- /dev/null
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am654.dtsi"
+#include "k3-am654-base-board-u-boot.dtsi"
+#include "k3-am654-base-board-ddr4-1600MHz.dtsi"
+#include "k3-am654-ddr.dtsi"
+
+/ {
+ compatible = "ti,am654-evm", "ti,am654";
+ model = "Texas Instruments AM654 R5 Base Board";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61>,
+ <&k3_pds 202>;
+ resets = <&k3_reset 202 0>;
+ assigned-clocks = <&k3_clks 202 0>;
+ assigned-clock-rates = <800000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ vtt_supply: vtt_supply {
+ compatible = "regulator-gpio";
+ regulator-name = "vtt";
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
+ states = <0 0x0 3300000 0x1>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_main {
+ timer1: timer@40400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x40400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cbass_mcu {
+ mcu_secproxy: secproxy@28380000 {
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>,
+ <0x0 0x2a480000 0x0 0x80000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx";
+ u-boot,dm-spl;
+ };
+
+ wkup_gpio0: wkup_gpio0@42110000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x42110000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,ngpio = <56>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k3_clks 59 0>;
+ clock-names = "gpio";
+ u-boot,dm-spl;
+ };
+
+};
+
+&dmsc {
+ mboxes= <&mcu_secproxy 7>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "okay";
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+ wkup_uart0_pins_default: wkup_uart0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /* (AB1) WKUP_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /* (AB5) WKUP_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ >;
+ u-boot,dm-spl;
+ };
+
+ wkup_vtt_pins_default: wkup_vtt_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7) /* WKUP_GPIO0_28 */
+ >;
+ u-boot,dm-spl;
+ };
+};
+
+&memorycontroller {
+ vtt-supply = <&vtt_supply>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_vtt_pins_default>;
+};
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index d5a7a8bb61cc418baadea9b5bf98200b1a22d158..bb33b4bc892bf2c13ad891fa43ab8e9e92b59599 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -193,6 +193,10 @@ lr .req x30
SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
SCR_EL3_NS_EN)
#endif
+
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+ orr \tmp, \tmp, #SCR_EL3_EA_EN
+#endif
msr scr_el3, \tmp
/* Return to the EL2_SP2 mode from EL3 */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index c1f87f9caf57a774152243db2b9e75be386e8bc7..aed2e3c51ef4b1a66984794264f7de58af707768 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -29,6 +29,7 @@
#define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
#define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
#define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
+#define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */
#define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
/*
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 0ca61210da7ed04a2d099e056d5c855cd3a4a1e5..f7fb77235cd642b734fdb17c60f0a4e1b2c9cd64 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -59,7 +59,7 @@
#endif
ENTRY(memcpy)
cmp r0, r1
- moveq pc, lr
+ bxeq lr
enter r4, lr
@@ -147,7 +147,8 @@ ENTRY(memcpy)
str1b r0, r4, cs, abort=21f
str1b r0, ip, cs, abort=21f
- exit r4, pc
+ exit r4, lr
+ bx lr
9: rsb ip, ip, #4
cmp ip, #2
@@ -256,7 +257,8 @@ ENTRY(memcpy)
.endm
.macro copy_abort_end
- ldmfd sp!, {r4, pc}
+ ldmfd sp!, {r4, lr}
+ bx lr
.endm
ENDPROC(memcpy)
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
index 99b0cc812dc3e2db7ade29b27473b3f0f13fde54..cd2272367b53a0df87e1cffee681270493dd353f 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -4,7 +4,7 @@
*
* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
+ * Copyright (C) 2018 Microchip Technology Inc.
*
* Watchdog Timer (WDT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
@@ -27,9 +27,13 @@ typedef struct at91_wdt {
#endif
+/* Watchdog Control Register */
+#define AT91_WDT_CR 0x00
#define AT91_WDT_CR_WDRSTT 1
#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */
+/* Watchdog Mode Register*/
+#define AT91_WDT_MR 0X04
#define AT91_WDT_MR_WDV(x) (x & 0xfff)
#define AT91_WDT_MR_WDFIEN 0x00001000
#define AT91_WDT_MR_WDRSTEN 0x00002000
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index 8bfb2a452b5e89b898697df2d1f9ee1600bcf558..6da6d41be2ecffc5cbe99b46e80a538e046f1683 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -11,7 +11,7 @@
#include <asm/arch/clk.h>
#include <spl.h>
-#if !defined(CONFIG_AT91SAM9_WATCHDOG)
+#if !defined(CONFIG_WDT_AT91)
void at91_disable_wdt(void)
{
struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index 8c368042a6b29a0ace586c7b17026f0b0a24f482..23ebaa99b169507efd6f14d9fab1ada91fd5dfa2 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -76,7 +76,7 @@ void __weak spl_board_init(void)
void board_init_f(ulong dummy)
{
lowlevel_clock_init();
-#if !defined(CONFIG_AT91SAM9_WATCHDOG)
+#if !defined(CONFIG_WDT_AT91)
at91_disable_wdt();
#endif
diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 597ff8c036736f206b61389b7945a61bfe7721d9..ef745c94775dc81f80d0fa19650b8244642625a0 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -98,7 +98,7 @@ void board_init_f(ulong dummy)
configure_2nd_sram_as_l2_cache();
#endif
-#if !defined(CONFIG_AT91SAM9_WATCHDOG)
+#if !defined(CONFIG_WDT_AT91)
/* disable watchdog */
at91_disable_wdt();
#endif
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 2df6197af7f3990f881581f5a697475070b867fe..e677a2e01b8986ee1206d1f19069fa3b483790be 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -47,5 +47,23 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
+config SYS_K3_KEY
+ string "Key used to generate x509 certificate"
+ help
+ This option enables to provide a custom key that can be used for
+ generating x509 certificate for spl binary. If not needed leave
+ it blank so that a random key is generated and used.
+
+config SYS_K3_BOOT_CORE_ID
+ int
+ default 16
+
+config SYS_K3_SPL_ATF
+ bool "Start Cortex-A from SPL"
+ depends on SPL && CPU_V7R
+ help
+ Enabling this will try to start Cortex-A (typically with ATF)
+ after SPL from R5.
+
source "board/ti/am65x/Kconfig"
endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index e9b7ee5210c34e560eee16e3a3037e6e8056bdb5..406dda3b023ad9391d0468e361952fe6f7127c32 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -5,3 +5,5 @@
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
+obj-$(CONFIG_CPU_V7R) += r5_mpu.o
+obj-y += common.o
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 68f0b8c011f028460ecb0ae712e29c840c1a0b3f..e2fe00c422f5afb795410af21d086ff4d97a87f0 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -10,6 +10,8 @@
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/hardware.h>
+#include "common.h"
+#include <dm.h>
#ifdef CONFIG_SPL_BUILD
static void mmr_unlock(u32 base, u32 partition)
@@ -56,6 +58,10 @@ static void store_boot_index_from_rom(void)
void board_init_f(ulong dummy)
{
+#if defined(CONFIG_K3_AM654_DDRSS)
+ struct udevice *dev;
+ int ret;
+#endif
/*
* Cannot delay this further as there is a chance that
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
@@ -65,11 +71,23 @@ void board_init_f(ulong dummy)
/* Make all control module registers accessible */
ctrl_mmr_unlock();
+#ifdef CONFIG_CPU_V7R
+ setup_k3_mpu_regions();
+#endif
+
/* Init DM early in-order to invoke system controller */
spl_early_init();
/* Prepare console output */
preloader_console_init();
+
+#ifdef CONFIG_K3_AM654_DDRSS
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return;
+ }
+#endif
}
u32 spl_boot_mode(const u32 boot_device)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
new file mode 100644
index 0000000000000000000000000000000000000000..cc89d4a29619331ceb14cd3fa743a7930ff43ed0
--- /dev/null
+++ b/arch/arm/mach-k3/common.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K3: Common Architecture initialization
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include "common.h"
+#include <dm.h>
+#include <remoteproc.h>
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ int ret;
+
+ /*
+ * It is assumed that remoteproc device 1 is the corresponding
+ * cortex A core which runs ATF. Make sure DT reflects the same.
+ */
+ ret = rproc_dev_init(1);
+ if (ret) {
+ printf("%s: ATF failed to Initialize on rproc: ret= %d\n",
+ __func__, ret);
+ hang();
+ }
+
+ ret = rproc_load(1, spl_image->entry_point, 0x200);
+ if (ret) {
+ printf("%s: ATF failed to load on rproc: ret= %d\n",
+ __func__, ret);
+ hang();
+ }
+
+ /* Add an extra newline to differentiate the ATF logs from SPL*/
+ printf("Starting ATF on ARM64 core...\n\n");
+
+ ret = rproc_start(1);
+ if (ret) {
+ printf("%s: ATF failed to start on rproc: ret= %d\n",
+ __func__, ret);
+ hang();
+ }
+
+ debug("ATF started. Wait indefiniely\n");
+ while (1)
+ asm volatile("wfe");
+}
+#endif
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac7e80d9af21f274eaeb294b18c72d61841d9a4e
--- /dev/null
+++ b/arch/arm/mach-k3/common.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: Architecture common definitions
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <asm/armv7_mpu.h>
+
+void setup_k3_mpu_regions(void);
diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 9b86ddc715fdefd96ee6fc2ba3fb86646d455a23..7fc0b3f357628fc83007ccfaf2505dd23b14da94 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -5,6 +5,65 @@
ifdef CONFIG_SPL_BUILD
+# Openssl is required to generate x509 certificate.
+# Error out if openssl is not available.
+ifeq ($(shell which openssl),)
+$(error "No openssl in $(PATH), consider installing openssl")
+endif
+
+SHA_VALUE= $(shell openssl dgst -sha512 -hex $(obj)/u-boot-spl.bin | sed -e "s/^.*= //g")
+IMAGE_SIZE= $(shell cat $(obj)/u-boot-spl.bin | wc -c)
+LOADADDR= $(shell echo $(CONFIG_SPL_TEXT_BASE) | sed -e "s/^0x//g")
+MAX_SIZE= $(shell printf "%d" $(CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE))
+
+# Parameters to get populated into the x509 template
+SED_OPTS= -e s/TEST_IMAGE_LENGTH/$(IMAGE_SIZE)/
+SED_OPTS+= -e s/TEST_IMAGE_SHA_VAL/$(SHA_VALUE)/
+SED_OPTS+= -e s/TEST_CERT_TYPE/1/ # CERT_TYPE_PRIMARY_IMAGE_BIN
+SED_OPTS+= -e s/TEST_BOOT_CORE/$(CONFIG_SYS_K3_BOOT_CORE_ID)/
+SED_OPTS+= -e s/TEST_BOOT_ARCH_WIDTH/32/
+SED_OPTS+= -e s/TEST_BOOT_ADDR/$(LOADADDR)/
+
+# Command to generate ecparam key
+quiet_cmd_genkey = OPENSSL $@
+cmd_genkey = openssl ecparam -out $@ -name prime256v1 -genkey
+
+# Command to generate x509 certificate
+quiet_cmd_gencert = OPENSSL $@
+cmd_gencert = cat $(srctree)/tools/k3_x509template.txt | sed $(SED_OPTS) > u-boot-spl-x509.txt; \
+ openssl req -new -x509 -key $(KEY) -nodes -outform DER -out $@ -config u-boot-spl-x509.txt -sha512
+
+# If external key is not provided, generate key using openssl.
+ifeq ($(CONFIG_SYS_K3_KEY), "")
+KEY=u-boot-spl-eckey.pem
+else
+KEY=$(patsubst "%",%,$(CONFIG_SYS_K3_KEY))
+endif
+
+u-boot-spl-eckey.pem: FORCE
+ $(call if_changed,genkey)
+
+# tiboot3.bin is mandated by ROM and ROM only supports R5 boot.
+# So restrict tiboot3.bin creation for CPU_V7R.
+ifdef CONFIG_CPU_V7R
+u-boot-spl-cert.bin: $(KEY) $(obj)/u-boot-spl.bin image_check FORCE
+ $(call if_changed,gencert)
+
+image_check: $(obj)/u-boot-spl.bin FORCE
+ @if [ $(IMAGE_SIZE) -gt $(MAX_SIZE) ]; then \
+ echo "===============================================" >&2; \
+ echo "ERROR: Final Image too big. " >&2; \
+ echo "$< size = $(IMAGE_SIZE), max size = $(MAX_SIZE)" >&2; \
+ echo "===============================================" >&2; \
+ exit 1; \
+ fi
+
+tiboot3.bin: u-boot-spl-cert.bin $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,cat)
+
+ALL-y += tiboot3.bin
+endif
+
ifdef CONFIG_ARM64
SPL_ITS := u-boot-spl-k3.its
$(SPL_ITS): FORCE
diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h b/arch/arm/mach-k3/include/mach/sys_proto.h
new file mode 100644
index 0000000000000000000000000000000000000000..0b2007981a498648742bcdf3185f49cda5e72955
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/sys_proto.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Andreas Dannenberg <dannenberg@ti.com>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound);
+
+#endif
diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c
new file mode 100644
index 0000000000000000000000000000000000000000..ee076ed87701f7e5cd8431a34cc443fdf2ada913
--- /dev/null
+++ b/arch/arm/mach-k3/r5_mpu.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K3: R5 MPU region definitions
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/kernel.h>
+#include "common.h"
+
+struct mpu_region_config k3_mpu_regions[16] = {
+ /*
+ * Make all 4GB as Device Memory and not executable. We are overriding
+ * it with next region for any requirement.
+ */
+ {0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED,
+ REGION_4GB},
+
+ /* SPL code area marking it as WB and Write allocate. */
+ {CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_8MB},
+
+ /* U-Boot's code area marking it as WB and Write allocate */
+ {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_2GB},
+ {0x0, 3, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 4, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 5, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 6, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 7, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 8, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 9, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 10, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 11, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 12, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 13, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 14, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 15, 0x0, 0x0, 0x0, 0x0},
+};
+
+void setup_k3_mpu_regions(void)
+{
+ setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions));
+}
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 024aa7c51220bb96f72b7a8858149c3dec728bce..2c6b42231230a1fe87df8dd15e2bc79494c298ee 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -727,6 +727,10 @@
sandbox_virtio2 {
compatible = "sandbox,virtio2";
};
+
+ pinctrl {
+ compatible = "sandbox,pinctrl";
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/board/broadcom/bcm968580xref/Kconfig b/board/broadcom/bcm968580xref/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..b5730367a2d276ad1c6d99a46e542aed83b83d3e
--- /dev/null
+++ b/board/broadcom/bcm968580xref/Kconfig
@@ -0,0 +1,17 @@
+if ARCH_BCM6858
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_BOARD
+ default "bcm968580xref"
+
+config SYS_CONFIG_NAME
+ default "broadcom_bcm968580xref"
+
+endif
+
+config TARGET_BCM968580XREF
+ bool "Support Broadcom bcm968580xref"
+ depends on ARCH_BCM6858
+ select ARM64
diff --git a/board/broadcom/bcm968580xref/MAINTAINERS b/board/broadcom/bcm968580xref/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..1ecdfbc0bbdf6fde190233a8ca34bc18bf37e1db
--- /dev/null
+++ b/board/broadcom/bcm968580xref/MAINTAINERS
@@ -0,0 +1,6 @@
+BROADCOM BCM968580XREF
+M: Philippe Reynes <philippe.reynes@softathome.com>
+S: Maintained
+F: board/broadcom/bcm968580xref/
+F: include/configs/broadcom_bcm968580xref.h
+F: configs/bcm968580_ram_defconfig
diff --git a/board/broadcom/bcm968580xref/Makefile b/board/broadcom/bcm968580xref/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..5cd393b1962912df4f3b2ec8c7a4ab5ae62c8ac5
--- /dev/null
+++ b/board/broadcom/bcm968580xref/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += bcm968580xref.o
diff --git a/board/broadcom/bcm968580xref/bcm968580xref.c b/board/broadcom/bcm968580xref/bcm968580xref.c
new file mode 100644
index 0000000000000000000000000000000000000000..2e547f5170889584cb198226de5d471061968b4b
--- /dev/null
+++ b/board/broadcom/bcm968580xref/bcm968580xref.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region broadcom_bcm968580xref_mem_map[] = {
+ {
+ /* RAM */
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 8UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* SoC */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0xff80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = broadcom_bcm968580xref_mem_map;
+#endif
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_mem_size_base() != 0)
+ printf("fdtdec_setup_mem_size_base() has failed\n");
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return 0;
+}
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 478e37285f121dd96b5f2c214d935daa2b263b81..9b6e0c4c21a2058ab8d0d97def3e5969017f2c27 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -380,10 +380,16 @@ M: Hauke Mehrtens <hauke@hauke-m.de>
S: Maintained
F: configs/orangepi_r1_defconfig
+PINEBOOK BOARD:
+M: Vasily Khoruzhick <anarsoul@gmail.com>
+S: Maintained
+F: configs/pinebook_defconfig
+
PINE64 BOARDS
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
F: configs/pine64_plus_defconfig
+F: configs/pine64-lts_defconfig
PINE H64 BOARD
M: Icenowy Zheng <icenowy@aosc.io>
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index 591600483e9a049f3d020fc3b8a01efde7174f6d..d4b36dbb42f3d68a2bee37da9c1cbc01a8421b32 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -12,6 +12,14 @@ config TARGET_AM654_A53_EVM
select ARM64
select SOC_K3_AM6
+config TARGET_AM654_R5_EVM
+ bool "TI K3 based AM654 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select SOC_K3_AM6
+ select K3_AM654_DDRSS
+ imply SYS_K3_SPL_ATF
+
endchoice
if TARGET_AM654_A53_EVM
@@ -26,3 +34,19 @@ config SYS_CONFIG_NAME
default "am65x_evm"
endif
+
+if TARGET_AM654_R5_EVM
+
+config SYS_BOARD
+ default "am65x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am65x_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/am65x/MAINTAINERS b/board/ti/am65x/MAINTAINERS
index ca1ce58f72aa42a0bfe4c713b9eef5e5ff68c1ef..7c52e7599e03993d91fac2aa4a94f3a4d8060cb9 100644
--- a/board/ti/am65x/MAINTAINERS
+++ b/board/ti/am65x/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/ti/am65x/
F: include/configs/am65x_evm.h
F: configs/am65x_evm_a53_defconfig
+F: configs/am65x_evm_r5_defconfig
diff --git a/board/ti/am65x/README b/board/ti/am65x/README
index e7f4ff657862cfeed8dfad868b5e7087acfd6412..0b82bd557b502fb6dbdfd2d1e5848a92ff326df3 100644
--- a/board/ti/am65x/README
+++ b/board/ti/am65x/README
@@ -37,13 +37,13 @@ instead use Flacon boot flow to reduce boot time.
| +--------+ | | |
| : | | |
| +--------+ | +-----------+ | |
-| | *rom* |----------|-->| Reset rls | | |
+| | *ROM* |----------|-->| Reset rls | | |
| +--------+ | +-----------+ | |
| | | | : | |
-| | rom | | : | |
+| | ROM | | : | |
| |services| | : | |
| | | | +-------------+ | |
-| | | | | *R5 rom* | | |
+| | | | | *R5 ROM* | | |
| | | | +-------------+ | |
| | |<---------|---|Load and auth| | |
| | | | | tiboot3.bin | | |
@@ -52,17 +52,25 @@ instead use Flacon boot flow to reduce boot time.
| | | | : | |
| | | | : | |
| | | | +-------------+ | |
-| | Start | | | *R5 SPL* | | |
-| | System | | +-------------+ | |
-| |Firmware|<---------|---|Load and auth| | |
-| +--------+ | | sysfw bin | | |
-| : | +-------------+ | |
-| +---------+ | | DDR | | |
-| | *SYSFW* | | | config | | |
-| +---------+ | +-------------+ | |
-| | |<--------|---| Load | | |
-| | | | | tispl.bin | | |
+| | | | | *R5 SPL* | | |
+| | | | +-------------+ | |
+| | | | | Load | | |
+| | | | | sysfw.itb | | |
+| | Start | | +-------------+ | |
+| | System |<---------|---| Start | | |
+| |Firmware| | | SYSFW | | |
+| +--------+ | +-------------+ | |
+| : | | | | |
+| +---------+ | | Load | | |
+| | *SYSFW* | | | system | | |
+| +---------+ | | Config data | | |
+| | |<--------|---| | | |
+| | | | +-------------+ | |
+| | | | | | | |
+| | | | | DDR | | |
+| | | | | config | | |
| | | | +-------------+ | |
+| | | | | | | |
| | |<--------|---| Start A53 | | |
| | | | | and Reset | | |
| | | | +-------------+ | |
@@ -82,7 +90,7 @@ instead use Flacon boot flow to reduce boot time.
| | | | | +-----------+ |
| | | | | : |
| | | | | +-----------+ |
-| | |<--------|-----------------------|---->| *u-boot* | |
+| | |<--------|-----------------------|---->| *U-Boot* | |
| | | | | +-----------+ |
| | | | | | prompt | |
| | | | | +-----------+ |
@@ -96,9 +104,8 @@ requests DMSC to get these services done as shown in the above diagram.
Sources:
--------
1. SYSFW:
- System Firmware repo is closed source and the binaries are delivered
- to users with NDA. Please contact TI to get the System Firmware
- Binary named ti-sci-firmware-am6x.bin that runs on AM65x SoC.
+ Tree: git://git.ti.com/processor-firmware/system-firmware-image-gen.git
+ Branch: master
2. ATF:
Tree: https://github.com/ARM-software/arm-trusted-firmware.git
@@ -115,9 +122,7 @@ Sources:
Build procedure:
----------------
1. SYSFW:
- ROM expects a signed binary that contains the X509 certificate. So
-the binary ti-sci-firmware-am6x.bin cannot be uses as-is and needs to be signed.
-Contact TI on the procedure to sign the system firmware binary.
+$ make CROSS_COMPILE=arm-linux-gnueabihf-
2. ATF:
$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
@@ -128,14 +133,79 @@ $ make PLATFORM=k3-am65x CFG_ARM64_core=y
4. U-Boot:
4.1. R5:
- TBD.
+$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5
+$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
4.2. A53:
$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53
-$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a53
+$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a53
Target Images
--------------
Copy the below images to an SD card and boot:
+- sysfw.itb from step 1
- tiboot3.bin from step 4.1
- tispl.bin, u-boot.img from 4.2
+
+Image formats:
+--------------
+
+- tiboot3.bin:
+ +-----------------------+
+ | X.509 |
+ | Certificate |
+ | +-------------------+ |
+ | | | |
+ | | R5 | |
+ | | u-boot-spl.bin | |
+ | | | |
+ | +-------------------+ |
+ | | | |
+ | | FIT header | |
+ | | +---------------+ | |
+ | | | | | |
+ | | | DTB 1...N | | |
+ | | +---------------+ | |
+ | +-------------------+ |
+ +-----------------------+
+
+- tispl.bin
+ +-----------------------+
+ | |
+ | FIT HEADER |
+ | +-------------------+ |
+ | | | |
+ | | A53 ATF | |
+ | +-------------------+ |
+ | | | |
+ | | A53 OPTEE | |
+ | +-------------------+ |
+ | | | |
+ | | A53 SPL | |
+ | +-------------------+ |
+ | | | |
+ | | SPL DTB 1...N | |
+ | +-------------------+ |
+ +-----------------------+
+
+- sysfw.itb
+ +-----------------------+
+ | |
+ | FIT HEADER |
+ | +-------------------+ |
+ | | | |
+ | | sysfw.bin | |
+ | +-------------------+ |
+ | | | |
+ | | board config | |
+ | +-------------------+ |
+ | | | |
+ | | PM config | |
+ | +-------------------+ |
+ | | | |
+ | | RM config | |
+ | +-------------------+ |
+ | | | |
+ | | Secure config | |
+ | +-------------------+ |
+ +-----------------------+
diff --git a/cmd/Kconfig b/cmd/Kconfig
index d609f9d1c96078de90a195253751a63c0b1853b0..e2973b3c514e48707936260f2bbe506568d042e0 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -953,6 +953,14 @@ config CMD_PCMCIA
about 1990. These devices are typically removable memory or network
cards using a standard 68-pin connector.
+config CMD_PINMUX
+ bool "pinmux - show pins muxing"
+ default y if PINCTRL
+ help
+ Parse all available pin-controllers and show pins muxing. This
+ is useful for debug purpoer to check the pin muxing and to know if
+ a pin is configured as a GPIO or as an alternate function.
+
config CMD_POWEROFF
bool "poweroff"
help
diff --git a/cmd/Makefile b/cmd/Makefile
index 12a1330b0629fd9e151510340101e2b5f363bf72..0534ddc67975d40afcccd2c148b87858ac94ec59 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -103,6 +103,7 @@ ifdef CONFIG_PCI
obj-$(CONFIG_CMD_PCI) += pci.o
endif
obj-y += pcmcia.o
+obj-$(CONFIG_CMD_PINMUX) += pinmux.o
obj-$(CONFIG_CMD_PXE) += pxe.o
obj-$(CONFIG_CMD_WOL) += wol.o
obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 60b438766d31b1659fe94e43b74dc3874f03697a..cbeba6ba28f771e3ce9ddf3d13efea6d9298350c 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
__maybe_unused
static void print_num(const char *name, ulong value)
{
- printf("%-12s= 0x%08lX\n", name, value);
+ printf("%-12s= 0x%0*lx\n", name, 2 * (int)sizeof(value), value);
}
__maybe_unused
@@ -348,7 +348,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
if (gd->fdt_blob)
- printf("fdt_blob = %p\n", gd->fdt_blob);
+ print_num("fdt_blob", (ulong)gd->fdt_blob);
return 0;
}
diff --git a/cmd/pinmux.c b/cmd/pinmux.c
new file mode 100644
index 0000000000000000000000000000000000000000..6c8ec5164d3ca5cfbb057513d537820aef8ba0dc
--- /dev/null
+++ b/cmd/pinmux.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
+
+#define LIMIT_DEVNAME 30
+
+static struct udevice *currdev;
+
+static int do_dev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *name;
+ int ret;
+
+ switch (argc) {
+ case 2:
+ name = argv[1];
+ ret = uclass_get_device_by_name(UCLASS_PINCTRL, name, &currdev);
+ if (ret) {
+ printf("Can't get the pin-controller: %s!\n", name);
+ return CMD_RET_FAILURE;
+ }
+ case 1:
+ if (!currdev) {
+ printf("Pin-controller device is not set!\n");
+ return CMD_RET_USAGE;
+ }
+
+ printf("dev: %s\n", currdev->name);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int show_pinmux(struct udevice *dev)
+{
+ char pin_name[PINNAME_SIZE];
+ char pin_mux[PINMUX_SIZE];
+ int pins_count;
+ int i;
+ int ret;
+
+ pins_count = pinctrl_get_pins_count(dev);
+
+ if (pins_count == -ENOSYS) {
+ printf("Ops get_pins_count not supported\n");
+ return pins_count;
+ }
+
+ for (i = 0; i < pins_count; i++) {
+ ret = pinctrl_get_pin_name(dev, i, pin_name, PINNAME_SIZE);
+ if (ret == -ENOSYS) {
+ printf("Ops get_pin_name not supported\n");
+ return ret;
+ }
+
+ ret = pinctrl_get_pin_muxing(dev, i, pin_mux, PINMUX_SIZE);
+ if (ret) {
+ printf("Ops get_pin_muxing error (%d)\n", ret);
+ return ret;
+ }
+
+ printf("%-*s: %-*s\n", PINNAME_SIZE, pin_name,
+ PINMUX_SIZE, pin_mux);
+ }
+
+ return 0;
+}
+
+static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *dev;
+ int ret = CMD_RET_USAGE;
+
+ if (currdev && (argc < 2 || strcmp(argv[1], "-a")))
+ return show_pinmux(currdev);
+
+ if (argc < 2 || strcmp(argv[1], "-a"))
+ return ret;
+
+ uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
+ /* insert a separator between each pin-controller display */
+ printf("--------------------------\n");
+ printf("%s:\n", dev->name);
+ ret = show_pinmux(dev);
+ if (ret < 0)
+ printf("Can't display pin muxing for %s\n",
+ dev->name);
+ }
+
+ return ret;
+}
+
+static int do_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *dev;
+
+ printf("| %-*.*s| %-*.*s| %s\n",
+ LIMIT_DEVNAME, LIMIT_DEVNAME, "Device",
+ LIMIT_DEVNAME, LIMIT_DEVNAME, "Driver",
+ "Parent");
+
+ uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
+ printf("| %-*.*s| %-*.*s| %s\n",
+ LIMIT_DEVNAME, LIMIT_DEVNAME, dev->name,
+ LIMIT_DEVNAME, LIMIT_DEVNAME, dev->driver->name,
+ dev->parent->name);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static cmd_tbl_t pinmux_subcmd[] = {
+ U_BOOT_CMD_MKENT(dev, 2, 1, do_dev, "", ""),
+ U_BOOT_CMD_MKENT(list, 1, 1, do_list, "", ""),
+ U_BOOT_CMD_MKENT(status, 2, 1, do_status, "", ""),
+};
+
+static int do_pinmux(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ cmd_tbl_t *cmd;
+
+ argc--;
+ argv++;
+
+ cmd = find_cmd_tbl(argv[0], pinmux_subcmd, ARRAY_SIZE(pinmux_subcmd));
+ if (!cmd || argc > cmd->maxargs)
+ return CMD_RET_USAGE;
+
+ return cmd->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(pinmux, CONFIG_SYS_MAXARGS, 1, do_pinmux,
+ "show pin-controller muxing",
+ "list - list UCLASS_PINCTRL devices\n"
+ "pinmux dev [pincontroller-name] - select pin-controller device\n"
+ "pinmux status [-a] - print pin-controller muxing [for all]\n"
+)
diff --git a/common/board_f.c b/common/board_f.c
index 96503ff8d3c36a12339de06b0f872f678118baec..f1a1432d869712cebd13654c72c14dc0f2bea073 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -91,7 +91,7 @@ static int init_func_watchdog_init(void)
{
# if defined(CONFIG_HW_WATCHDOG) && \
(defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
- defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
+ defined(CONFIG_SH) || \
defined(CONFIG_DESIGNWARE_WATCHDOG) || \
defined(CONFIG_IMX_WATCHDOG))
hw_watchdog_init();
diff --git a/common/image-sig.c b/common/image-sig.c
index 5a269d3289bfcf72d7ad0fd5aeff7862f4badf11..5d860e1266379356a0f6ae4d0bf437abb6441a98 100644
--- a/common/image-sig.c
+++ b/common/image-sig.c
@@ -334,6 +334,11 @@ int fit_config_check_sig(const void *fit, int noffset, int required_keynode,
return -1;
}
+ if (prop && prop_len > 0 && prop[prop_len - 1] != '\0') {
+ *err_msgp = "hashed-nodes property must be null-terminated";
+ return -1;
+ }
+
/* Add a sanity check here since we are using the stack */
if (count > IMAGE_MAX_HASHED_NODES) {
*err_msgp = "Number of hashed nodes exceeds maximum";
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 882163f8c13afeb8cb8760d361338d49a5b0fc74..14805575ab6fc08de62f9ed291ed5b74b8fccbd2 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
@@ -34,9 +33,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1920k(u-boot),256k(u-boot-env),8m(kernel),512k(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am3517-evm"
-CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM_PCA953X=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..237b9e8229bf280b0e8028061975b981587b2a82
--- /dev/null
+++ b/configs/am65x_evm_r5_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SOC_K3_AM6=y
+CONFIG_TARGET_AM654_R5_EVM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USE_BOOTCOMMAND=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_GPIO=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_K3_ARASAN=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_K3=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
diff --git a/configs/bcm968580_ram_defconfig b/configs/bcm968580_ram_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..abe90ee75fb0daf0b489d939ceab7d6351812ca2
--- /dev/null
+++ b/configs/bcm968580_ram_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCM6858=y
+CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_TARGET_BCM968580XREF=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref"
+# CONFIG_NET is not set
+CONFIG_BLK=y
+CONFIG_CLK=y
+CONFIG_FIRMWARE=y
+# CONFIG_MMC is not set
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_BCM6858_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_REGEX=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 9167a9450d769b0a3ec0032970763ee3780c43a9..2e59686291b73ed7921201eae6128b0d669b980d 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_GPIO_SUPPORT=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index b1e7c35fa99e7e315ab703e016d19048a954931e..a1af2f1342f5b590031e016f906946236d128e81 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index a23f6a33d6d7beaaca29cc5dc3a8153aaff730f3..80219eeacfa00d3dcaeaffab4ec8fe36f2a9e6fc 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -29,9 +30,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit"
-CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index f28ca5bcbf34722b75dc1bdb7046a7de5a044bf0..8a8c7147c3a35fc52c152d2951eafc7ad228fe6d 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -29,9 +30,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit"
-CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 45e5b504f78969c4b8992cb8fa1bf86739c03ec9..969387a37cb7499d60af5131995290e3ee2b120b 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -29,9 +30,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
-CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index e733584ebe48ead84e452914e535e1e33d2ea2aa..396543e56bcc8e454b2529f8734c633f6597b81a 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -28,9 +29,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
-CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 0b6234fbd9c39e6a8e389a6c535a9635dd86754d..699e2e230ab329237a7687b4cdd998d15a05b8ac 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_PICOSAM9G45=y
@@ -39,3 +40,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_WDT=y
+CONFIG_WDT_AT91=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index cf6f2757cae28e010fa4bb179e3dbca89bec98f5..e9c2b6350991241dbfc7f1da2afdc0d508fc481d 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -59,3 +59,6 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_EFI_LOADER is not set
+CONFIG_WDT=y
+CONFIG_WDT_AT91=y
+CONFIG_AT91_HW_WDT_TIMEOUT=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index ee5da43ccbaf8adaa013349dc0176f7524585f0b..e53e075d48250bc21e77583e5c1f68e9d2b23fa7 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -61,3 +61,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0908
CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
+CONFIG_WDT=y
+CONFIG_WDT_AT91=y
+CONFIG_AT91_HW_WDT_TIMEOUT=y
diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig
index 33591d73e0d1bcb63ca8590ec33fa33ae86cc4b9..9d881e5d41ab381f08688711a11f4e4006fb32ca 100644
--- a/configs/wb45n_defconfig
+++ b/configs/wb45n_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_WB45N=y
diff --git a/doc/README.at91 b/doc/README.at91
index 67412136eeba1760b2d117fb1f468eb1a0168d38..39dd5632baa94ed5529caf98fa09e99cb0fd1a03 100644
--- a/doc/README.at91
+++ b/doc/README.at91
@@ -171,4 +171,4 @@ III. Watchdog support
your code (make sure not to disable it in AT91Bootstrap for instance).
In the U-Boot configuration, the AT91 watchdog support is enabled using
- the CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG options.
+ the CONFIG_WDT and CONFIG_WDT_AT91 options.
diff --git a/doc/README.watchdog b/doc/README.watchdog
index 7097c8766b437a232908055758cbbf0d5ce3cacd..f23c923910a6775af930d1489cacaa87e2289d0d 100644
--- a/doc/README.watchdog
+++ b/doc/README.watchdog
@@ -14,7 +14,7 @@ CONFIG_WATCHDOG_TIMEOUT_MSECS
If not given, will default to maximum timeout. This would
be 128000 msec for i.mx31/35/5x/6x.
-CONFIG_AT91SAM9_WATCHDOG
+CONFIG_WDT_AT91
Available for AT91SAM9 to service the watchdog.
CONFIG_FTWDT010_WATCHDOG
diff --git a/doc/device-tree-bindings/ram/k3-am654-ddrss.txt b/doc/device-tree-bindings/ram/k3-am654-ddrss.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4ed731c52422909f16eeec7fbf5787967a29692e
--- /dev/null
+++ b/doc/device-tree-bindings/ram/k3-am654-ddrss.txt
@@ -0,0 +1,46 @@
+Texas Instruments' K3 AM654 DDRSS
+=================================
+
+K3 based AM654 devices has DDR memory subsystem that comprises
+Synopys DDR controller, Synopsis DDR phy and wrapper logic to
+integrate these blocks into the device. This DDR subsystem
+provides an interface to external SDRAM devices. This DDRSS driver
+adds support for the initialization of the external SDRAM devices by
+configuring the DDRSS registers and using the buitin PHY
+initialization routines.
+
+DDRSS device node:
+==================
+Required properties:
+--------------------
+- compatible: Shall be: "ti,am654-ddrss"
+- reg-names ss - Map the sub system wrapper logic region
+ ctl - Map the controller region
+ phy - Map the PHY region
+- reg: Contains the register map per reg-names.
+- power-domains: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the DDRSS device id
+ value. This property is as per the binding,
+ doc/device-tree-bindings/power/ti,sci-pm-domain.txt
+- clocks: Must contain an entry for enabling DDR clock. Should
+ be defined as per the appropriate clock bindings consumer
+ usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
+
+
+Optional Properties:
+--------------------
+- clock-frequency: Frequency at which DDR pll should be locked.
+ If not provided, default frequency will be used.
+
+Example (AM65x):
+================
+ memory-controller: memory-controller@298e000 {
+ compatible = "ti,am654-ddrss";
+ reg = <0x0298e000 0x200>,
+ <0x02980000 0x4000>,
+ <0x02988000 0x2000>;
+ reg-names = "ss", "ctl", "phy";
+ clocks = <&k3_clks 20 0>;
+ power-domains = <&k3_pds 20>;
+ u-boot,dm-spl;
+ };
diff --git a/doc/device-tree-bindings/w1-eeprom/ds2502.txt b/doc/device-tree-bindings/w1-eeprom/ds2502.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7f05fc432e0ff757ed9f9ec8dd0d68e6d7dce3e6
--- /dev/null
+++ b/doc/device-tree-bindings/w1-eeprom/ds2502.txt
@@ -0,0 +1,33 @@
+Maxim DS2502 driver device binding - one wire protocol add only memory from Maxim
+=======================
+
+This memory needs to be connected to a onewire bus, as a child node.
+The bus will read the device serial number and match this node with a found
+device on the bus
+Also check doc/device-tree-bindings/w1 for onewire bus drivers
+
+Driver:
+- drivers/w1-eeprom/ds2502.c
+
+Ds2502 device-tree node properties:
+Required:
+* compatible = "maxim,ds2502"
+
+Optional:
+* none
+
+Example:
+ eeprom1: eeprom@0 {
+ compatible = "maxim,ds2502";
+ };
+
+Example with parent bus:
+ onewire {
+ compatible = "fsl,imx53-owire";
+ reg = <0x63fa4000 0x4000>;
+
+ eeprom1: eeprom@0 {
+ compatible = "maxim,ds2502";
+ };
+ };
+
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 2b15978e141a35ab706ee448b540d86f3c0310ef..04b369aa5a1e6aead2961ae46eda1bfd1570ad75 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -243,10 +243,6 @@ int clk_set_defaults(struct udevice *dev)
{
int ret;
- /* If this is running pre-reloc state, don't take any action. */
- if (!(gd->flags & GD_FLG_RELOC))
- return 0;
-
debug("%s(%s)\n", __func__, dev_read_name(dev));
ret = clk_set_default_parents(dev);
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 6cfcde8918c4dc4dfba1e722e82ccb1d9ec6b16b..d9c5719a878d75abdd76b51a81970936693e38b7 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -562,6 +562,19 @@ int uclass_next_device(struct udevice **devp)
return uclass_get_device_tail(dev, ret, devp);
}
+int uclass_next_device_err(struct udevice **devp)
+{
+ int ret;
+
+ ret = uclass_next_device(devp);
+ if (ret)
+ return ret;
+ else if (!*devp)
+ return -ENODEV;
+
+ return 0;
+}
+
int uclass_first_device_check(enum uclass_id id, struct udevice **devp)
{
int ret;
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 0bb484498a8e5f4ad77bb2f2e99ce82ca131d6e6..341527acc5e8e52abb4800ccca9b34ce08cf361a 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -130,6 +130,25 @@ static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
return ret;
}
+static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+ int ret = 0;
+
+ if (info->gpio_count <= 8) {
+ ret = dm_i2c_write(dev, reg, val, 1);
+ } else if (info->gpio_count <= 16) {
+ ret = dm_i2c_write(dev, reg << 1, val, info->bank_count);
+ } else if (info->gpio_count == 40) {
+ /* Auto increment */
+ ret = dm_i2c_write(dev, (reg << 3) | 0x80, val, info->bank_count);
+ } else {
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
static int pca953x_is_output(struct udevice *dev, int offset)
{
struct pca953x_info *info = dev_get_platdata(dev);
@@ -251,6 +270,7 @@ static int pca953x_probe(struct udevice *dev)
int ret;
int size;
const u8 *tmp;
+ u8 val[MAX_BANK];
addr = dev_read_addr(dev);
if (addr == 0)
@@ -296,6 +316,14 @@ static int pca953x_probe(struct udevice *dev)
snprintf(name, sizeof(name), "gpio@%x_", info->addr);
}
+ /* Clear the polarity registers to no invert */
+ memset(val, 0, MAX_BANK);
+ ret = pca953x_write_regs(dev, PCA953X_INVERT, val);
+ if (ret < 0) {
+ dev_err(dev, "Error writing invert register\n");
+ return ret;
+ }
+
str = strdup(name);
if (!str)
return -ENOMEM;
diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c
index b903dc46b33e967e88d44d25d878e5df9d260ea8..a690c437ebc67bf63a6f9b1044c420e16ae5c2c2 100644
--- a/drivers/gpio/stm32f7_gpio.c
+++ b/drivers/gpio/stm32f7_gpio.c
@@ -65,11 +65,31 @@ static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
return 0;
}
+static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int bits_index = MODE_BITS(offset);
+ int mask = MODE_BITS_MASK << bits_index;
+ u32 mode;
+
+ mode = (readl(®s->moder) & mask) >> bits_index;
+ if (mode == STM32_GPIO_MODE_OUT)
+ return GPIOF_OUTPUT;
+ if (mode == STM32_GPIO_MODE_IN)
+ return GPIOF_INPUT;
+ if (mode == STM32_GPIO_MODE_AN)
+ return GPIOF_UNUSED;
+
+ return GPIOF_FUNC;
+}
+
static const struct dm_gpio_ops gpio_stm32_ops = {
.direction_input = stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.get_value = stm32_gpio_get_value,
.set_value = stm32_gpio_set_value,
+ .get_function = stm32_gpio_get_function,
};
static int gpio_stm32_probe(struct udevice *dev)
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 36ec610c8ec696cdf01e2daf9ecf9afcacef6c3f..3872364d6bf59454cc26b5f19fdb0629c2c13c8d 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -58,7 +58,7 @@ struct stm32_i2c_regs {
#define STM32_I2C_CR2_ADD10 BIT(11)
#define STM32_I2C_CR2_RD_WRN BIT(10)
#define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
-#define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK))
+#define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK)
#define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
#define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
#define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
@@ -197,7 +197,7 @@ struct stm32_i2c_priv {
int speed;
};
-static struct stm32_i2c_spec i2c_specs[] = {
+static const struct stm32_i2c_spec i2c_specs[] = {
[STM32_I2C_SPEED_STANDARD] = {
.rate = STANDARD_RATE,
.rate_min = 8000,
@@ -236,7 +236,7 @@ static struct stm32_i2c_spec i2c_specs[] = {
},
};
-static struct stm32_i2c_setup stm32f7_setup = {
+static const struct stm32_i2c_setup stm32f7_setup = {
.rise_time = STM32_I2C_RISE_TIME_DEFAULT,
.fall_time = STM32_I2C_FALL_TIME_DEFAULT,
.dnf = STM32_I2C_DNF_DEFAULT,
@@ -255,7 +255,7 @@ static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
}
static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
- struct i2c_msg *msg, bool stop)
+ struct i2c_msg *msg, bool stop)
{
struct stm32_i2c_regs *regs = i2c_priv->regs;
u32 cr2 = readl(®s->cr2);
@@ -299,7 +299,7 @@ static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
*/
static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
- struct i2c_msg *msg, bool stop)
+ struct i2c_msg *msg, bool stop)
{
struct stm32_i2c_regs *regs = i2c_priv->regs;
u32 cr2 = readl(®s->cr2);
@@ -317,7 +317,7 @@ static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
}
static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
- u32 flags, u32 *status)
+ u32 flags, u32 *status)
{
struct stm32_i2c_regs *regs = i2c_priv->regs;
u32 time_start = get_timer(0);
@@ -392,7 +392,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
}
static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
- struct i2c_msg *msg, bool stop)
+ struct i2c_msg *msg, bool stop)
{
struct stm32_i2c_regs *regs = i2c_priv->regs;
u32 status;
@@ -465,7 +465,7 @@ static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
}
static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
- int nmsgs)
+ int nmsgs)
{
struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
int ret;
@@ -594,6 +594,7 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
for (l = 0; l < STM32_SCLL_MAX; l++) {
u32 tscl_l = (l + 1) * prescaler + tsync;
+
if ((tscl_l < i2c_specs[setup->speed].l_min) ||
(i2cclk >=
((tscl_l - af_delay_min - dnf_delay) / 4))) {
@@ -634,8 +635,8 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
}
static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
- struct stm32_i2c_setup *setup,
- struct stm32_i2c_timings *output)
+ struct stm32_i2c_setup *setup,
+ struct stm32_i2c_timings *output)
{
struct stm32_i2c_timings *v, *_v;
struct list_head solutions;
@@ -643,28 +644,28 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
if (setup->speed >= STM32_I2C_SPEED_END) {
pr_err("%s: speed out of bound {%d/%d}\n", __func__,
- setup->speed, STM32_I2C_SPEED_END - 1);
+ setup->speed, STM32_I2C_SPEED_END - 1);
return -EINVAL;
}
if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
(setup->fall_time > i2c_specs[setup->speed].fall_max)) {
pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
- __func__,
- setup->rise_time, i2c_specs[setup->speed].rise_max,
- setup->fall_time, i2c_specs[setup->speed].fall_max);
+ __func__,
+ setup->rise_time, i2c_specs[setup->speed].rise_max,
+ setup->fall_time, i2c_specs[setup->speed].fall_max);
return -EINVAL;
}
if (setup->dnf > STM32_I2C_DNF_MAX) {
pr_err("%s: DNF out of bound %d/%d\n", __func__,
- setup->dnf, STM32_I2C_DNF_MAX);
+ setup->dnf, STM32_I2C_DNF_MAX);
return -EINVAL;
}
if (setup->speed_freq > i2c_specs[setup->speed].rate) {
pr_err("%s: Freq {%d/%d}\n", __func__,
- setup->speed_freq, i2c_specs[setup->speed].rate);
+ setup->speed_freq, i2c_specs[setup->speed].rate);
return -EINVAL;
}
@@ -693,7 +694,7 @@ exit:
}
static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
- struct stm32_i2c_timings *timing)
+ struct stm32_i2c_timings *timing)
{
struct stm32_i2c_setup *setup = i2c_priv->setup;
int ret = 0;
diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c
index b7bb96a4583e3bee9a2926d038956cffe48fe173..baa5f8302aeb8c050cbbdacf819fc3e02e095e8d 100644
--- a/drivers/misc/fs_loader.c
+++ b/drivers/misc/fs_loader.c
@@ -55,11 +55,9 @@ static int select_fs_dev(struct device_platdata *plat)
node = ofnode_get_by_phandle(plat->phandlepart.phandle);
- int of_offset = ofnode_to_offset(node);
-
struct udevice *dev;
- ret = device_get_global_by_of_offset(of_offset, &dev);
+ ret = device_get_global_by_ofnode(node, &dev);
if (!ret) {
struct blk_desc *desc = blk_get_by_device(dev);
if (desc) {
@@ -190,8 +188,9 @@ static int fw_get_filesystem_firmware(struct device_platdata *plat,
ret = fs_read(fw_priv->name, (ulong)map_to_sysmem(firmware->data),
fw_priv->offset, firmware->size, &actread);
+
if (ret) {
- debug("Error: %d Failed to read %s from flash %lld != %d.\n",
+ debug("Error: %d Failed to read %s from flash %lld != %zu.\n",
ret, fw_priv->name, actread, firmware->size);
} else {
ret = actread;
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index 5d4ffea608d9ba5bec7d9a23591cd9660f1ce123..79d1489dc72c81add92ca4024df019bde40d33fc 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -82,6 +82,10 @@ struct lpc32xx_nand_mlc_registers {
static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
= (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
+#if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
+#define CONFIG_SYS_MAX_NAND_CHIPS 1
+#endif
+
#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
/**
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index 99f6e15f4e071f704b01dc2c7ce5a5b62e1e9035..8615b112a21ffeb746f939de5855ec5102b49f42 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
@@ -2,13 +2,12 @@
/*
* LPC32xx SLC NAND flash controller driver
*
- * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ * (C) Copyright 2015-2018 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (c) 2015 Tyco Fire Protection Products.
*
* Hardware ECC support original source code
* Copyright (C) 2008 by NXP Semiconductors
* Author: Kevin Wells
- *
- * Copyright (c) 2015 Tyco Fire Protection Products.
*/
#include <common.h>
@@ -22,10 +21,6 @@
#include <asm/arch/dma.h>
#include <asm/arch/cpu.h>
-#if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD)
-#warning "DMA support in SPL image is not tested"
-#endif
-
struct lpc32xx_nand_slc_regs {
u32 data;
u32 addr;
@@ -78,16 +73,14 @@ struct lpc32xx_nand_slc_regs {
* Note: For large page devices, the default layouts are used. */
static struct nand_ecclayout lpc32xx_nand_oob_16 = {
.eccbytes = 6,
- .eccpos = {10, 11, 12, 13, 14, 15},
+ .eccpos = { 10, 11, 12, 13, 14, 15, },
.oobfree = {
- {.offset = 0,
- . length = 4},
- {.offset = 6,
- . length = 4}
- }
+ { .offset = 0, .length = 4, },
+ { .offset = 6, .length = 4, },
+ }
};
-#if defined(CONFIG_DMA_LPC32XX)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
/*
@@ -165,7 +158,7 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
}
-#if defined(CONFIG_DMA_LPC32XX)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
/*
* Prepares DMA descriptors for NAND RD/WR operations
* If the size is < 256 Bytes then it is assumed to be
@@ -324,7 +317,6 @@ static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
if (unlikely(ret < 0))
BUG();
-
/* Wait for NAND to be ready */
while (!lpc32xx_nand_dev_ready(mtd))
;
@@ -404,46 +396,18 @@ int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
return ret2;
}
-#endif
-#if defined(CONFIG_DMA_LPC32XX)
static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
lpc32xx_nand_xfer(mtd, buf, len, 1);
}
-#else
-static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- while (len-- > 0)
- *buf++ = readl(&lpc32xx_nand_slc_regs->data);
-}
-#endif
-static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
-{
- return readl(&lpc32xx_nand_slc_regs->data);
-}
-
-#if defined(CONFIG_DMA_LPC32XX)
static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf,
int len)
{
lpc32xx_nand_xfer(mtd, buf, len, 0);
}
-#else
-static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
- while (len-- > 0)
- writel(*buf++, &lpc32xx_nand_slc_regs->data);
-}
-#endif
-
-static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
-{
- writel(byte, &lpc32xx_nand_slc_regs->data);
-}
-#if defined(CONFIG_DMA_LPC32XX)
/* Reuse the logic from "nand_read_page_hwecc()" */
static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
@@ -511,8 +475,30 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
return 0;
}
+#else
+static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ while (len-- > 0)
+ *buf++ = readl(&lpc32xx_nand_slc_regs->data);
+}
+
+static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ while (len-- > 0)
+ writel(*buf++, &lpc32xx_nand_slc_regs->data);
+}
#endif
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+ return readl(&lpc32xx_nand_slc_regs->data);
+}
+
+static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
+{
+ writel(byte, &lpc32xx_nand_slc_regs->data);
+}
+
/*
* LPC32xx has only one SLC NAND controller, don't utilize
* CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
@@ -520,7 +506,7 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
*/
int board_nand_init(struct nand_chip *lpc32xx_chip)
{
-#if defined(CONFIG_DMA_LPC32XX)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
int ret;
/* Acquire a channel for our use */
@@ -543,7 +529,7 @@ int board_nand_init(struct nand_chip *lpc32xx_chip)
lpc32xx_chip->read_byte = lpc32xx_read_byte;
lpc32xx_chip->write_byte = lpc32xx_write_byte;
-#if defined(CONFIG_DMA_LPC32XX)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
/* Hardware ECC calculation is supported when DMA driver is selected */
lpc32xx_chip->ecc.mode = NAND_ECC_HW;
diff --git a/drivers/pinctrl/pinctrl-sandbox.c b/drivers/pinctrl/pinctrl-sandbox.c
index 755ac08bdf72cd880e9ce6413065192f4e3ffc96..0786afe747fc6668cb24044f8ced3ffbff931e8e 100644
--- a/drivers/pinctrl/pinctrl-sandbox.c
+++ b/drivers/pinctrl/pinctrl-sandbox.c
@@ -17,6 +17,14 @@ static const char * const sandbox_pins[] = {
"W1"
};
+static const char * const sandbox_pins_muxing[] = {
+ "I2C SCL",
+ "I2C SDA",
+ "Uart TX",
+ "Uart RX",
+ "1-wire gpio",
+};
+
static const char * const sandbox_groups[] = {
"i2c",
"serial_a",
@@ -56,6 +64,15 @@ static const char *sandbox_get_pin_name(struct udevice *dev, unsigned selector)
return sandbox_pins[selector];
}
+static int sandbox_get_pin_muxing(struct udevice *dev,
+ unsigned int selector,
+ char *buf, int size)
+{
+ snprintf(buf, size, "%s", sandbox_pins_muxing[selector]);
+
+ return 0;
+}
+
static int sandbox_get_groups_count(struct udevice *dev)
{
return ARRAY_SIZE(sandbox_groups);
@@ -123,6 +140,7 @@ static int sandbox_pinconf_group_set(struct udevice *dev,
const struct pinctrl_ops sandbox_pinctrl_ops = {
.get_pins_count = sandbox_get_pins_count,
.get_pin_name = sandbox_get_pin_name,
+ .get_pin_muxing = sandbox_get_pin_muxing,
.get_groups_count = sandbox_get_groups_count,
.get_group_name = sandbox_get_group_name,
.get_functions_count = sandbox_get_functions_count,
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index c38bb212ed74bd74c0f7a3f7194fa1f7b7f24546..6db0445067079dcb2bdc986d7a1b6cd49710da98 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -249,6 +249,40 @@ int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index)
return ops->get_gpio_mux(dev, banknum, index);
}
+int pinctrl_get_pins_count(struct udevice *dev)
+{
+ struct pinctrl_ops *ops = pinctrl_get_ops(dev);
+
+ if (!ops->get_pins_count)
+ return -ENOSYS;
+
+ return ops->get_pins_count(dev);
+}
+
+int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf,
+ int size)
+{
+ struct pinctrl_ops *ops = pinctrl_get_ops(dev);
+
+ if (!ops->get_pin_name)
+ return -ENOSYS;
+
+ snprintf(buf, size, ops->get_pin_name(dev, selector));
+
+ return 0;
+}
+
+int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf,
+ int size)
+{
+ struct pinctrl_ops *ops = pinctrl_get_ops(dev);
+
+ if (!ops->get_pin_muxing)
+ return -ENOSYS;
+
+ return ops->get_pin_muxing(dev, selector, buf, size);
+}
+
/**
* pinconfig_post_bind() - post binding for PINCTRL uclass
* Recursively bind child nodes as pinconfig devices in case of full pinctrl.
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 31285cdd5784da2f915f52a5fd2fe4c41079d067..6d4117d941f6ec4c4d8035334e9d2dbe83496232 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -14,6 +14,194 @@ DECLARE_GLOBAL_DATA_PTR;
#define OTYPE_MSK 1
#define AFR_MASK 0xF
+#ifndef CONFIG_SPL_BUILD
+struct stm32_pinctrl_priv {
+ int pinctrl_ngpios;
+ struct list_head gpio_dev;
+};
+
+struct stm32_gpio_bank {
+ struct udevice *gpio_dev;
+ struct list_head list;
+};
+
+#define MAX_PIN_PER_BANK 16
+
+static char pin_name[PINNAME_SIZE];
+#define PINMUX_MODE_COUNT 5
+static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
+ "gpio input",
+ "gpio output",
+ "analog",
+ "unknown",
+ "alt function",
+};
+
+static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ u32 af;
+ u32 alt_shift = (offset % 8) * 4;
+ u32 alt_index = offset / 8;
+
+ af = (readl(®s->afr[alt_index]) &
+ GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
+
+ return af;
+}
+
+static int stm32_pinctrl_get_pins_count(struct udevice *dev)
+{
+ struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv;
+ struct stm32_gpio_bank *gpio_bank;
+
+ /*
+ * if get_pins_count has already been executed once on this
+ * pin-controller, no need to run it again
+ */
+ if (priv->pinctrl_ngpios)
+ return priv->pinctrl_ngpios;
+
+ /*
+ * walk through all banks to retrieve the pin-controller
+ * pins number
+ */
+ list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
+ uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
+
+ priv->pinctrl_ngpios += uc_priv->gpio_count;
+ }
+
+ return priv->pinctrl_ngpios;
+}
+
+static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
+ unsigned int selector)
+{
+ struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_bank *gpio_bank;
+ struct gpio_dev_priv *uc_priv;
+ int first_pin = 0;
+
+ /* look up for the bank which owns the requested pin */
+ list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
+ uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
+
+ if (selector < (first_pin + uc_priv->gpio_count))
+ /* we found the bank */
+ return gpio_bank->gpio_dev;
+
+ first_pin += uc_priv->gpio_count;
+ }
+
+ return NULL;
+}
+
+static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ struct gpio_dev_priv *uc_priv;
+ struct udevice *gpio_dev;
+
+ /* look up for the bank which owns the requested pin */
+ gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
+ if (!gpio_dev) {
+ snprintf(pin_name, PINNAME_SIZE, "Error");
+ } else {
+ uc_priv = dev_get_uclass_priv(gpio_dev);
+
+ snprintf(pin_name, PINNAME_SIZE, "%s%d",
+ uc_priv->bank_name,
+ selector % MAX_PIN_PER_BANK);
+ }
+
+ return pin_name;
+}
+
+static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
+ unsigned int selector,
+ char *buf,
+ int size)
+{
+ struct udevice *gpio_dev;
+ const char *label;
+ int gpio_pin;
+ int mode;
+ int af_num;
+
+ /* look up for the bank which owns the requested pin */
+ gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
+
+ if (!gpio_dev)
+ return -ENODEV;
+
+ /* translate pin-controller pin number to gpio pin number */
+ gpio_pin = selector % MAX_PIN_PER_BANK;
+
+ mode = gpio_get_raw_function(gpio_dev, gpio_pin, &label);
+
+ dev_dbg(dev, "selector = %d gpio_pin = %d mode = %d\n",
+ selector, gpio_pin, mode);
+
+ switch (mode) {
+ case GPIOF_UNKNOWN:
+ /* should never happen */
+ return -EINVAL;
+ case GPIOF_UNUSED:
+ snprintf(buf, size, "%s", pinmux_mode[mode]);
+ break;
+ case GPIOF_FUNC:
+ af_num = stm32_pinctrl_get_af(gpio_dev, gpio_pin);
+ snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
+ break;
+ case GPIOF_OUTPUT:
+ case GPIOF_INPUT:
+ snprintf(buf, size, "%s %s",
+ pinmux_mode[mode], label ? label : "");
+ break;
+ }
+
+ return 0;
+}
+
+int stm32_pinctrl_probe(struct udevice *dev)
+{
+ struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
+ struct udevice *gpio_dev;
+ struct udevice *child;
+ struct stm32_gpio_bank *gpio_bank;
+ int ret;
+
+ INIT_LIST_HEAD(&priv->gpio_dev);
+
+ /*
+ * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
+ * a list with all gpio device reference which belongs to the
+ * current pin-controller. This list is used to find pin_name and
+ * pin muxing
+ */
+ list_for_each_entry(child, &dev->child_head, sibling_node) {
+ ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
+ &gpio_dev);
+ if (ret < 0)
+ continue;
+
+ gpio_bank = malloc(sizeof(*gpio_bank));
+ if (!gpio_bank) {
+ dev_err(dev, "Not enough memory\n");
+ return -ENOMEM;
+ }
+
+ gpio_bank->gpio_dev = gpio_dev;
+ list_add_tail(&gpio_bank->list, &priv->gpio_dev);
+ }
+
+ return 0;
+}
+#endif
+
static int stm32_gpio_config(struct gpio_desc *desc,
const struct stm32_gpio_ctl *ctl)
{
@@ -182,6 +370,11 @@ static struct pinctrl_ops stm32_pinctrl_ops = {
#else /* PINCTRL_FULL */
.set_state_simple = stm32_pinctrl_set_state_simple,
#endif /* PINCTRL_FULL */
+#ifndef CONFIG_SPL_BUILD
+ .get_pin_name = stm32_pinctrl_get_pin_name,
+ .get_pins_count = stm32_pinctrl_get_pins_count,
+ .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
+#endif
};
static const struct udevice_id stm32_pinctrl_ids[] = {
@@ -195,9 +388,13 @@ static const struct udevice_id stm32_pinctrl_ids[] = {
};
U_BOOT_DRIVER(pinctrl_stm32) = {
- .name = "pinctrl_stm32",
- .id = UCLASS_PINCTRL,
- .of_match = stm32_pinctrl_ids,
- .ops = &stm32_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
+ .name = "pinctrl_stm32",
+ .id = UCLASS_PINCTRL,
+ .of_match = stm32_pinctrl_ids,
+ .ops = &stm32_pinctrl_ops,
+ .bind = dm_scan_fdt_dev,
+#ifndef CONFIG_SPL_BUILD
+ .probe = stm32_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
+#endif
};
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 54bb4b419f0c321aaf80e35e88a1c5f20f42dbb2..fbf7d7b20fbf1fb18b664095a2a4a766fad45fa6 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -43,4 +43,15 @@ config MPC83XX_SDRAM
the RAM through the use of SPD (Serial Presence Detect) is supported
via device tree settings.
+config K3_AM654_DDRSS
+ bool "Enable AM654 DDRSS support"
+ depends on RAM && SOC_K3_AM6
+ help
+ K3 based AM654 devices has DDR memory subsystem that comprises
+ Synopys DDR controller, Synopsis DDR phy and wrapper logic to
+ intergrate these blocks into the device. This DDR subsystem
+ provides an interface to external SDRAM devices. Enabling this
+ config add support for the initialization of the external
+ SDRAM devices connected to DDR subsystem.
+
source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index cfba57f0fdf0842e33d132fd124b10617b28ff6c..e14c1cf592208a3fd19007df35c7c7eeb3aaba82 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
+
+obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c
new file mode 100644
index 0000000000000000000000000000000000000000..7957f678a1b06228d9bde4f2b33d459eeab1718b
--- /dev/null
+++ b/drivers/ram/k3-am654-ddrss.c
@@ -0,0 +1,825 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' AM654 DDRSS driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <dm.h>
+#include <asm/arch/sys_proto.h>
+#include <power/regulator.h>
+#include "k3-am654-ddrss.h"
+
+#define LDELAY 10000
+
+/* DDRSS PHY configuration register fixed values */
+#define DDRSS_DDRPHY_RANKIDR_RANK0 0
+
+/**
+ * struct am654_ddrss_desc - Description of ddrss integration.
+ * @dev: DDRSS device pointer
+ * @ddrss_ss_cfg: DDRSS wrapper logic region base address
+ * @ddrss_ctl_cfg: DDRSS controller region base address
+ * @ddrss_phy_cfg: DDRSS PHY region base address
+ * @ddrss_clk: DDRSS clock description
+ * @vtt_supply: VTT Supply regulator
+ * @ddrss_pwrdmn: DDRSS power domain description
+ * @params: SDRAM configuration parameters
+ */
+struct am654_ddrss_desc {
+ struct udevice *dev;
+ void __iomem *ddrss_ss_cfg;
+ void __iomem *ddrss_ctl_cfg;
+ void __iomem *ddrss_phy_cfg;
+ struct clk ddrss_clk;
+ struct udevice *vtt_supply;
+ struct power_domain ddrcfg_pwrdmn;
+ struct power_domain ddrdata_pwrdmn;
+ struct ddrss_params params;
+};
+
+static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
+{
+ return readl(addr + offset);
+}
+
+static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
+ u32 data)
+{
+ debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
+ writel(data, addr + offset);
+}
+
+#define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
+#define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
+
+static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
+{
+ return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
+}
+
+/**
+ * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
+ *
+ * After detecting the DDR type this function will pause until the
+ * initialization is complete. Each DDR type has mask of multiple bits.
+ * The size of the field depends on the DDR Type. If the initialization
+ * does not complete and error will be returned and will cause the boot to halt.
+ *
+ */
+static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
+{
+ u32 val, mask;
+
+ val = am654_ddrss_get_type(ddrss);
+
+ switch (val) {
+ case DDR_TYPE_LPDDR4:
+ case DDR_TYPE_DDR4:
+ mask = DDR4_STAT_MODE_MASK;
+ break;
+ case DDR_TYPE_DDR3:
+ mask = DDR3_STAT_MODE_MASK;
+ break;
+ default:
+ printf("Unsupported DDR type 0x%x\n", val);
+ return -EINVAL;
+ }
+
+ if (!wait_on_value(mask, DDR_MODE_NORMAL,
+ ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+/**
+ * am654_ddrss_ctrl_configuration() - Configure Controller specific registers
+ * @dev: corresponding ddrss device
+ */
+static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
+{
+ struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
+ struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
+ struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
+ struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
+ struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
+ u32 val;
+
+ debug("%s: DDR controller register configuration started\n", __func__);
+
+ ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
+ ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
+ ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
+
+ ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
+ ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
+ ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
+ ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
+
+ ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
+ ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
+ ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
+ ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
+ ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
+ ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
+ ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
+
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
+
+ ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
+
+ ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
+ ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
+
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
+
+ ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
+ ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
+
+ /* Disable refreshes */
+ val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
+ val |= 0x01;
+ ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
+
+ debug("%s: DDR controller configuration completed\n", __func__);
+}
+
+#define ddrss_phy_writel(off, val) \
+ do { \
+ ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \
+ sdelay(10); /* Delay at least 20 clock cycles */ \
+ } while (0)
+
+#define ddrss_phy_readl(off) \
+ ({ \
+ u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \
+ sdelay(10); /* Delay at least 20 clock cycles */ \
+ val; \
+ })
+
+/**
+ * am654_ddrss_phy_configuration() - Configure PHY specific registers
+ * @ddrss: corresponding ddrss device
+ */
+static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
+{
+ struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
+ struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
+ struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
+ struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
+ struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
+
+ debug("%s: DDR phy register configuration started\n", __func__);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
+ ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
+ ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
+ ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
+ ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
+ ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
+ ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
+ ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
+ ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
+ ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
+ ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
+ ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
+ ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
+ ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
+ ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
+ ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
+ ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
+ ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
+ ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
+ ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
+ ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
+
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
+
+ debug("%s: DDR phy register configuration completed\n", __func__);
+}
+
+static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
+ u32 init_value, u32 sts_mask,
+ u32 err_mask)
+{
+ int ret;
+
+ ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
+
+ sdelay(5); /* Delay at least 10 clock cycles */
+
+ if (!wait_on_value(sts_mask, sts_mask,
+ ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
+ return -ETIMEDOUT;
+
+ sdelay(16); /* Delay at least 32 clock cycles */
+
+ ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
+ debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
+ if (ret & err_mask)
+ return -EINVAL;
+
+ return 0;
+}
+
+int write_leveling(struct am654_ddrss_desc *ddrss)
+{
+ int ret;
+
+ debug("%s: Write leveling started\n", __func__);
+
+ ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
+ PGSR0_WLERR_MASK);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s: ERROR: Write leveling timedout\n",
+ __func__);
+ else
+ printf("%s:ERROR: Write leveling failed\n", __func__);
+ return ret;
+ }
+
+ debug("%s: Write leveling completed\n", __func__);
+ return 0;
+}
+
+int read_dqs_training(struct am654_ddrss_desc *ddrss)
+{
+ int ret;
+
+ debug("%s: Read DQS training started\n", __func__);
+
+ ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
+ PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s: ERROR: Read DQS timedout\n", __func__);
+ else
+ printf("%s:ERROR: Read DQS Gate training failed\n",
+ __func__);
+ return ret;
+ }
+
+ debug("%s: Read DQS training completed\n", __func__);
+ return 0;
+}
+
+int rest_training(struct am654_ddrss_desc *ddrss)
+{
+ int ret;
+ u32 val;
+ u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
+
+ debug("%s: Rest of the training started\n", __func__);
+
+ debug("%s: Write Leveling adjustment\n", __func__);
+ ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
+ PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s:ERROR: Write Leveling adjustment timedout\n",
+ __func__);
+ else
+ printf("%s: ERROR: Write Leveling adjustment failed\n",
+ __func__);
+ return ret;
+ }
+
+ debug("%s: Read Deskew adjustment\n", __func__);
+ ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
+ PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s: ERROR: Read Deskew timedout\n", __func__);
+ else
+ printf("%s: ERROR: Read Deskew failed\n", __func__);
+ return ret;
+ }
+
+ debug("%s: Write Deskew adjustment\n", __func__);
+ ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
+ PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s: ERROR: Write Deskew timedout\n", __func__);
+ else
+ printf("%s: ERROR: Write Deskew failed\n", __func__);
+ return ret;
+ }
+
+ debug("%s: Read Eye training\n", __func__);
+ ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
+ PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s: ERROR: Read Eye training timedout\n",
+ __func__);
+ else
+ printf("%s: ERROR: Read Eye training failed\n",
+ __func__);
+ return ret;
+ }
+
+ debug("%s: Write Eye training\n", __func__);
+ ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
+ PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s: ERROR: Write Eye training timedout\n",
+ __func__);
+ else
+ printf("%s: ERROR: Write Eye training failed\n",
+ __func__);
+ return ret;
+ }
+
+ debug("%s: VREF training\n", __func__);
+ ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
+ PGSR0_VERR_MASK);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ printf("%s: ERROR: VREF training timedout\n", __func__);
+ else
+ printf("%s: ERROR: VREF training failed\n", __func__);
+ return ret;
+ }
+
+ ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
+ dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
+ dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
+ dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
+ dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
+
+ rddly = dgsl0;
+ if (dgsl1 < rddly)
+ rddly = dgsl1;
+ if (dgsl2 < rddly)
+ rddly = dgsl2;
+ if (dgsl3 < rddly)
+ rddly = dgsl3;
+
+ rddly += 5;
+
+ /* Update rddly based on dgsl values */
+ val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
+ val |= (rddly << 20);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
+
+ val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
+ val |= (rddly << 20);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
+
+ val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
+ val |= (rddly << 20);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
+
+ val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
+ val |= (rddly << 20);
+ ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
+
+ /*
+ * Add system latency derived from training back into rd2wr and wr2rd
+ * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
+ * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
+ */
+
+ /* Select rank 0 */
+ ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
+
+ dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
+ dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
+ dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
+ dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
+
+ /* Find maximum value across all bytes */
+ rd2wr_wr2rd = dgsl0;
+ if (dgsl1 > rd2wr_wr2rd)
+ rd2wr_wr2rd = dgsl1;
+ if (dgsl2 > rd2wr_wr2rd)
+ rd2wr_wr2rd = dgsl2;
+ if (dgsl3 > rd2wr_wr2rd)
+ rd2wr_wr2rd = dgsl3;
+
+ rd2wr_wr2rd >>= 1;
+
+ /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
+ /* Clear VSWCTL.sw_done */
+ ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
+ ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
+ /* Adjust rd2wr */
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
+ ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
+ (rd2wr_wr2rd << 8));
+ /* Adjust wr2rd */
+ ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
+ ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
+ rd2wr_wr2rd);
+ /* Set VSWCTL.sw_done */
+ ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
+ ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
+ /* Wait until settings are applied */
+ while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
+ /* Do nothing */
+ };
+
+ debug("%s: Rest of the training completed\n", __func__);
+ return 0;
+}
+
+/**
+ * am654_ddrss_init() - Initialization sequence for enabling the SDRAM
+ * device attached to ddrss.
+ * @dev: corresponding ddrss device
+ *
+ * Does all the initialization sequence that is required to get attached
+ * ddr in a working state. After this point, ddr should be accessible.
+ * Return: 0 if all went ok, else corresponding error message.
+ */
+static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
+{
+ int ret;
+
+ debug("%s(ddrss=%p)\n", __func__, ddrss);
+
+ ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF);
+
+ am654_ddrss_ctrl_configuration(ddrss);
+
+ /* Release the reset to the controller */
+ clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
+ SS_CTL_REG_CTL_ARST_MASK);
+
+ am654_ddrss_phy_configuration(ddrss);
+
+ ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
+ if (ret) {
+ dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
+ return ret;
+ }
+
+ ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
+ PGSR0_DRAM_INIT_MASK, 0);
+ if (ret) {
+ dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
+ return ret;
+ }
+
+ ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
+ if (ret) {
+ printf("%s: ERROR: DRAM Wait for init complete timedout\n",
+ __func__);
+ return ret;
+ }
+
+ ret = write_leveling(ddrss);
+ if (ret)
+ return ret;
+
+ ret = read_dqs_training(ddrss);
+ if (ret)
+ return ret;
+
+ ret = rest_training(ddrss);
+ if (ret)
+ return ret;
+
+ /* Enabling refreshes after training is done */
+ ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
+ ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
+
+ /* Disable PUBMODE after training is done */
+ ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
+ ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
+
+ return 0;
+}
+
+/**
+ * am654_ddrss_power_on() - Enable power and clocks for ddrss
+ * @dev: corresponding ddrss device
+ *
+ * Tries to enable all the corresponding clocks to the ddrss and sets it
+ * to the right frequency and then power on the ddrss.
+ * Return: 0 if all went ok, else corresponding error message.
+ */
+static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
+{
+ int ret;
+
+ debug("%s(ddrss=%p)\n", __func__, ddrss);
+
+ ret = clk_enable(&ddrss->ddrss_clk);
+ if (ret) {
+ dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
+ if (ret) {
+ dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
+ if (ret) {
+ dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
+ return ret;
+ }
+
+ /* VTT enable */
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ device_get_supply_regulator(ddrss->dev, "vtt-supply",
+ &ddrss->vtt_supply);
+ ret = regulator_set_value(ddrss->vtt_supply, 3300000);
+ if (ret)
+ return ret;
+ debug("VTT regulator enabled\n");
+#endif
+
+ return 0;
+}
+
+/**
+ * am654_ddrss_ofdata_to_priv() - generate private data from device tree
+ * @dev: corresponding ddrss device
+ *
+ * Return: 0 if all went ok, else corresponding error message.
+ */
+static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
+{
+ struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
+ phys_addr_t reg;
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
+ if (ret) {
+ dev_err(dev, "clk_get failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
+ if (ret) {
+ dev_err(dev, "power_domain_get() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
+ if (ret) {
+ dev_err(dev, "power_domain_get() failed: %d\n", ret);
+ return ret;
+ }
+
+ reg = devfdt_get_addr_name(dev, "ss");
+ if (reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "No reg property for DDRSS wrapper logic\n");
+ return -EINVAL;
+ }
+ ddrss->ddrss_ss_cfg = (void *)reg;
+
+ reg = devfdt_get_addr_name(dev, "ctl");
+ if (reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "No reg property for Controller region\n");
+ return -EINVAL;
+ }
+ ddrss->ddrss_ctl_cfg = (void *)reg;
+
+ reg = devfdt_get_addr_name(dev, "phy");
+ if (reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "No reg property for PHY region\n");
+ return -EINVAL;
+ }
+ ddrss->ddrss_phy_cfg = (void *)reg;
+
+ ret = dev_read_u32_array(dev, "ti,ctl-reg",
+ (u32 *)&ddrss->params.ctl_reg,
+ sizeof(ddrss->params.ctl_reg) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,ctl-reg params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,ctl-crc",
+ (u32 *)&ddrss->params.ctl_crc,
+ sizeof(ddrss->params.ctl_crc) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,ctl-crc params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,ctl-ecc",
+ (u32 *)&ddrss->params.ctl_ecc,
+ sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,ctl-ecc params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,ctl-map",
+ (u32 *)&ddrss->params.ctl_map,
+ sizeof(ddrss->params.ctl_map) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,ctl-map params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,ctl-pwr",
+ (u32 *)&ddrss->params.ctl_pwr,
+ sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,ctl-pwr params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,ctl-timing",
+ (u32 *)&ddrss->params.ctl_timing,
+ sizeof(ddrss->params.ctl_timing) /
+ sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,ctl-timing params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,phy-cfg",
+ (u32 *)&ddrss->params.phy_cfg,
+ sizeof(ddrss->params.phy_cfg) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,phy-cfg params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,phy-ctl",
+ (u32 *)&ddrss->params.phy_ctrl,
+ sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,phy-ctl params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,phy-ioctl",
+ (u32 *)&ddrss->params.phy_ioctl,
+ sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,phy-ioctl params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,phy-timing",
+ (u32 *)&ddrss->params.phy_timing,
+ sizeof(ddrss->params.phy_timing) /
+ sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,phy-timing params\n");
+ return ret;
+ }
+
+ ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
+ sizeof(ddrss->params.phy_zq) / sizeof(u32));
+ if (ret) {
+ dev_err(dev, "Cannot read ti,phy-zq params\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+/**
+ * am654_ddrss_probe() - Basic probe
+ * @dev: corresponding ddrss device
+ *
+ * Return: 0 if all went ok, else corresponding error message
+ */
+static int am654_ddrss_probe(struct udevice *dev)
+{
+ struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ ret = am654_ddrss_ofdata_to_priv(dev);
+ if (ret)
+ return ret;
+
+ ddrss->dev = dev;
+ ret = am654_ddrss_power_on(ddrss);
+ if (ret)
+ return ret;
+
+ ret = am654_ddrss_init(ddrss);
+
+ return ret;
+}
+
+static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
+{
+ return 0;
+}
+
+static struct ram_ops am654_ddrss_ops = {
+ .get_info = am654_ddrss_get_info,
+};
+
+static const struct udevice_id am654_ddrss_ids[] = {
+ { .compatible = "ti,am654-ddrss" },
+ { }
+};
+
+U_BOOT_DRIVER(am654_ddrss) = {
+ .name = "am654_ddrss",
+ .id = UCLASS_RAM,
+ .of_match = am654_ddrss_ids,
+ .ops = &am654_ddrss_ops,
+ .probe = am654_ddrss_probe,
+ .priv_auto_alloc_size = sizeof(struct am654_ddrss_desc),
+};
diff --git a/drivers/ram/k3-am654-ddrss.h b/drivers/ram/k3-am654-ddrss.h
new file mode 100644
index 0000000000000000000000000000000000000000..78d73cd9fc989f8ae629dc5b670401c2cc6d1ea7
--- /dev/null
+++ b/drivers/ram/k3-am654-ddrss.h
@@ -0,0 +1,1189 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * AM654: DDRSS Register definitions and structures.
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ */
+
+#ifndef __K3_AM654_DDRSS_H
+#define __K3_AM654_DDRSS_H
+
+/* DDRSS subsystem wrapper logic registers */
+#define DDRSS_SS_ID_REV_REG 0x00000000
+#define DDRSS_SS_CTL_REG 0x00000004
+#define DDRSS_V2H_CTL_REG 0x00000020
+
+#define SS_CTL_REG_CTL_ARST_SHIFT 0x0
+#define SS_CTL_REG_CTL_ARST_MASK BIT(SS_CTL_REG_CTL_ARST_SHIFT)
+
+/* DDRSS controller configuration registers */
+#define DDRSS_DDRCTL_MSTR 0x00000000
+#define DDRSS_DDRCTL_STAT 0x00000004
+#define DDRSS_DDRCTL_MRCTRL0 0x00000010
+#define DDRSS_DDRCTL_MRCTRL1 0x00000014
+#define DDRSS_DDRCTL_MRSTAT 0x00000018
+#define DDRSS_DDRCTL_MRCTRL2 0x0000001C
+#define DDRSS_DDRCTL_DERATEEN 0x00000020
+#define DDRSS_DDRCTL_DERATEINT 0x00000024
+#define DDRSS_DDRCTL_MSTR2 0x00000028
+#define DDRSS_DDRCTL_PWRCTL 0x00000030
+#define DDRSS_DDRCTL_PWRTMG 0x00000034
+#define DDRSS_DDRCTL_HWLPCTL 0x00000038
+#define DDRSS_DDRCTL_RFSHCTL0 0x00000050
+#define DDRSS_DDRCTL_RFSHCTL1 0x00000054
+#define DDRSS_DDRCTL_RFSHCTL2 0x00000058
+#define DDRSS_DDRCTL_RFSHCTL3 0x00000060
+#define DDRSS_DDRCTL_RFSHTMG 0x00000064
+#define DDRSS_DDRCTL_ECCCFG0 0x00000070
+#define DDRSS_DDRCTL_ECCCFG1 0x00000074
+#define DDRSS_DDRCTL_ECCSTAT 0x00000078
+#define DDRSS_DDRCTL_ECCCLR 0x0000007C
+#define DDRSS_DDRCTL_ECCERRCNT 0x00000080
+#define DDRSS_DDRCTL_ECCCADDR0 0x00000084
+#define DDRSS_DDRCTL_ECCCADDR1 0x00000088
+#define DDRSS_DDRCTL_ECCCSYN0 0x0000008C
+#define DDRSS_DDRCTL_ECCCSYN2 0x00000094
+#define DDRSS_DDRCTL_ECCBITMASK0 0x00000098
+#define DDRSS_DDRCTL_ECCBITMASK2 0x000000A0
+#define DDRSS_DDRCTL_ECCUADDR0 0x000000A4
+#define DDRSS_DDRCTL_ECCUADDR1 0x000000A8
+#define DDRSS_DDRCTL_ECCUSYN0 0x000000AC
+#define DDRSS_DDRCTL_ECCUSYN2 0x000000B4
+#define DDRSS_DDRCTL_ECCPOISONADDR0 0x000000B8
+#define DDRSS_DDRCTL_ECCPOISONADDR1 0x000000BC
+#define DDRSS_DDRCTL_CRCPARCTL0 0x000000C0
+#define DDRSS_DDRCTL_CRCPARCTL1 0x000000C4
+#define DDRSS_DDRCTL_CRCPARCTL2 0x000000C8
+#define DDRSS_DDRCTL_CRCPARSTAT 0x000000CC
+#define DDRSS_DDRCTL_INIT0 0x000000D0
+#define DDRSS_DDRCTL_INIT1 0x000000D4
+#define DDRSS_DDRCTL_INIT2 0x000000D8
+#define DDRSS_DDRCTL_INIT3 0x000000DC
+#define DDRSS_DDRCTL_INIT4 0x000000E0
+#define DDRSS_DDRCTL_INIT5 0x000000E4
+#define DDRSS_DDRCTL_INIT6 0x000000E8
+#define DDRSS_DDRCTL_INIT7 0x000000EC
+#define DDRSS_DDRCTL_DIMMCTL 0x000000F0
+#define DDRSS_DDRCTL_RANKCTL 0x000000F4
+#define DDRSS_DDRCTL_DRAMTMG0 0x00000100
+#define DDRSS_DDRCTL_DRAMTMG1 0x00000104
+#define DDRSS_DDRCTL_DRAMTMG2 0x00000108
+#define DDRSS_DDRCTL_DRAMTMG3 0x0000010C
+#define DDRSS_DDRCTL_DRAMTMG4 0x00000110
+#define DDRSS_DDRCTL_DRAMTMG5 0x00000114
+#define DDRSS_DDRCTL_DRAMTMG6 0x00000118
+#define DDRSS_DDRCTL_DRAMTMG7 0x0000011C
+#define DDRSS_DDRCTL_DRAMTMG8 0x00000120
+#define DDRSS_DDRCTL_DRAMTMG9 0x00000124
+#define DDRSS_DDRCTL_DRAMTMG10 0x00000128
+#define DDRSS_DDRCTL_DRAMTMG11 0x0000012C
+#define DDRSS_DDRCTL_DRAMTMG12 0x00000130
+#define DDRSS_DDRCTL_DRAMTMG13 0x00000134
+#define DDRSS_DDRCTL_DRAMTMG14 0x00000138
+#define DDRSS_DDRCTL_DRAMTMG15 0x0000013C
+#define DDRSS_DDRCTL_DRAMTMG17 0x00000144
+#define DDRSS_DDRCTL_ZQCTL0 0x00000180
+#define DDRSS_DDRCTL_ZQCTL1 0x00000184
+#define DDRSS_DDRCTL_ZQCTL2 0x00000188
+#define DDRSS_DDRCTL_ZQSTAT 0x0000018C
+#define DDRSS_DDRCTL_DFITMG0 0x00000190
+#define DDRSS_DDRCTL_DFITMG1 0x00000194
+#define DDRSS_DDRCTL_DFILPCFG0 0x00000198
+#define DDRSS_DDRCTL_DFILPCFG1 0x0000019C
+#define DDRSS_DDRCTL_DFIUPD0 0x000001A0
+#define DDRSS_DDRCTL_DFIUPD1 0x000001A4
+#define DDRSS_DDRCTL_DFIUPD2 0x000001A8
+#define DDRSS_DDRCTL_DFIMISC 0x000001B0
+#define DDRSS_DDRCTL_DFITMG2 0x000001B4
+#define DDRSS_DDRCTL_DFITMG3 0x000001B8
+#define DDRSS_DDRCTL_DFISTAT 0x000001BC
+#define DDRSS_DDRCTL_DBICTL 0x000001C0
+#define DDRSS_DDRCTL_DFIPHYMSTR 0x000001C4
+#define DDRSS_DDRCTL_ADDRMAP0 0x00000200
+#define DDRSS_DDRCTL_ADDRMAP1 0x00000204
+#define DDRSS_DDRCTL_ADDRMAP2 0x00000208
+#define DDRSS_DDRCTL_ADDRMAP3 0x0000020C
+#define DDRSS_DDRCTL_ADDRMAP4 0x00000210
+#define DDRSS_DDRCTL_ADDRMAP5 0x00000214
+#define DDRSS_DDRCTL_ADDRMAP6 0x00000218
+#define DDRSS_DDRCTL_ADDRMAP7 0x0000021C
+#define DDRSS_DDRCTL_ADDRMAP8 0x00000220
+#define DDRSS_DDRCTL_ADDRMAP9 0x00000224
+#define DDRSS_DDRCTL_ADDRMAP10 0x00000228
+#define DDRSS_DDRCTL_ADDRMAP11 0x0000022C
+#define DDRSS_DDRCTL_ODTCFG 0x00000240
+#define DDRSS_DDRCTL_ODTMAP 0x00000244
+#define DDRSS_DDRCTL_SCHED 0x00000250
+#define DDRSS_DDRCTL_SCHED1 0x00000254
+#define DDRSS_DDRCTL_PERFHPR1 0x0000025C
+#define DDRSS_DDRCTL_PERFLPR1 0x00000264
+#define DDRSS_DDRCTL_PERFWR1 0x0000026C
+#define DDRSS_DDRCTL_DQMAP0 0x00000280
+#define DDRSS_DDRCTL_DQMAP1 0x00000284
+#define DDRSS_DDRCTL_DQMAP4 0x00000290
+#define DDRSS_DDRCTL_DQMAP5 0x00000294
+#define DDRSS_DDRCTL_DBG0 0x00000300
+#define DDRSS_DDRCTL_DBG1 0x00000304
+#define DDRSS_DDRCTL_DBGCAM 0x00000308
+#define DDRSS_DDRCTL_DBGCMD 0x0000030C
+#define DDRSS_DDRCTL_DBGSTAT 0x00000310
+#define DDRSS_DDRCTL_SWCTL 0x00000320
+#define DDRSS_DDRCTL_SWSTAT 0x00000324
+#define DDRSS_DDRCTL_ADVECCINDEX 0x00000374
+#define DDRSS_DDRCTL_ECCPOISONPAT0 0x0000037C
+#define DDRSS_DDRCTL_ECCPOISONPAT2 0x00000384
+#define DDRSS_DDRCTL_CAPARPOISONCTL 0x000003A0
+#define DDRSS_DDRCTL_CAPARPOISONSTAT 0x000003A4
+#define DDRSS_DDRCTL_DERATEEN_SHDW 0x00002020
+#define DDRSS_DDRCTL_DERATEINT_SHDW 0x00002024
+#define DDRSS_DDRCTL_RFSHCTL0_SHDW 0x00002050
+#define DDRSS_DDRCTL_RFSHTMG_SHDW 0x00002064
+#define DDRSS_DDRCTL_INIT3_SHDW 0x000020DC
+#define DDRSS_DDRCTL_INIT4_SHDW 0x000020E0
+#define DDRSS_DDRCTL_INIT6_SHDW 0x000020E8
+#define DDRSS_DDRCTL_INIT7_SHDW 0x000020EC
+#define DDRSS_DDRCTL_DRAMTMG0_SHDW 0x00002100
+#define DDRSS_DDRCTL_DRAMTMG1_SHDW 0x00002104
+#define DDRSS_DDRCTL_DRAMTMG2_SHDW 0x00002108
+#define DDRSS_DDRCTL_DRAMTMG3_SHDW 0x0000210C
+#define DDRSS_DDRCTL_DRAMTMG4_SHDW 0x00002110
+#define DDRSS_DDRCTL_DRAMTMG5_SHDW 0x00002114
+#define DDRSS_DDRCTL_DRAMTMG6_SHDW 0x00002118
+#define DDRSS_DDRCTL_DRAMTMG7_SHDW 0x0000211C
+#define DDRSS_DDRCTL_DRAMTMG8_SHDW 0x00002120
+#define DDRSS_DDRCTL_DRAMTMG9_SHDW 0x00002124
+#define DDRSS_DDRCTL_DRAMTMG10_SHDW 0x00002128
+#define DDRSS_DDRCTL_DRAMTMG11_SHDW 0x0000212C
+#define DDRSS_DDRCTL_DRAMTMG12_SHDW 0x00002130
+#define DDRSS_DDRCTL_DRAMTMG13_SHDW 0x00002134
+#define DDRSS_DDRCTL_DRAMTMG14_SHDW 0x00002138
+#define DDRSS_DDRCTL_DRAMTMG15_SHDW 0x0000213C
+#define DDRSS_DDRCTL_ZQCTL0_SHDW 0x00002180
+#define DDRSS_DDRCTL_DFITMG0_SHDW 0x00002190
+#define DDRSS_DDRCTL_DFITMG1_SHDW 0x00002194
+#define DDRSS_DDRCTL_DFITMG2_SHDW 0x000021B4
+#define DDRSS_DDRCTL_DFITMG3_SHDW 0x000021B8
+#define DDRSS_DDRCTL_ODTCFG_SHDW 0x00002240
+
+#define MSTR_DDR_TYPE_MASK GENMASK(5, 0)
+#define DDR_TYPE_LPDDR4 0x20
+#define DDR_TYPE_DDR4 0x10
+#define DDR_TYPE_DDR3 0x1
+
+#define DDR3_STAT_MODE_MASK GENMASK(1, 0)
+#define DDR4_STAT_MODE_MASK GENMASK(2, 0)
+#define DDR_MODE_NORMAL 0x1
+
+/* DDRSS PHY configuration registers */
+#define DDRSS_DDRPHY_RIDR 0x00000000
+#define DDRSS_DDRPHY_PIR 0x00000004
+#define DDRSS_DDRPHY_PGCR0 0x00000010
+#define DDRSS_DDRPHY_PGCR1 0x00000014
+#define DDRSS_DDRPHY_PGCR2 0x00000018
+#define DDRSS_DDRPHY_PGCR3 0x0000001C
+#define DDRSS_DDRPHY_PGCR4 0x00000020
+#define DDRSS_DDRPHY_PGCR5 0x00000024
+#define DDRSS_DDRPHY_PGCR6 0x00000028
+#define DDRSS_DDRPHY_PGCR7 0x0000002C
+#define DDRSS_DDRPHY_PGSR0 0x00000030
+#define DDRSS_DDRPHY_PGSR1 0x00000034
+#define DDRSS_DDRPHY_PGSR2 0x00000038
+#define DDRSS_DDRPHY_PTR0 0x00000040
+#define DDRSS_DDRPHY_PTR1 0x00000044
+#define DDRSS_DDRPHY_PTR2 0x00000048
+#define DDRSS_DDRPHY_PTR3 0x0000004C
+#define DDRSS_DDRPHY_PTR4 0x00000050
+#define DDRSS_DDRPHY_PTR5 0x00000054
+#define DDRSS_DDRPHY_PTR6 0x00000058
+#define DDRSS_DDRPHY_PLLCR0 0x00000068
+#define DDRSS_DDRPHY_PLLCR1 0x0000006C
+#define DDRSS_DDRPHY_PLLCR2 0x00000070
+#define DDRSS_DDRPHY_PLLCR3 0x00000074
+#define DDRSS_DDRPHY_PLLCR4 0x00000078
+#define DDRSS_DDRPHY_PLLCR5 0x0000007C
+#define DDRSS_DDRPHY_DXCCR 0x00000088
+#define DDRSS_DDRPHY_DSGCR 0x00000090
+#define DDRSS_DDRPHY_ODTCR 0x00000098
+#define DDRSS_DDRPHY_AACR 0x000000A0
+#define DDRSS_DDRPHY_GPR0 0x000000C0
+#define DDRSS_DDRPHY_GPR1 0x000000C4
+#define DDRSS_DDRPHY_DCR 0x00000100
+#define DDRSS_DDRPHY_DTPR0 0x00000110
+#define DDRSS_DDRPHY_DTPR1 0x00000114
+#define DDRSS_DDRPHY_DTPR2 0x00000118
+#define DDRSS_DDRPHY_DTPR3 0x0000011C
+#define DDRSS_DDRPHY_DTPR4 0x00000120
+#define DDRSS_DDRPHY_DTPR5 0x00000124
+#define DDRSS_DDRPHY_DTPR6 0x00000128
+#define DDRSS_DDRPHY_RDIMMGCR0 0x00000140
+#define DDRSS_DDRPHY_RDIMMGCR1 0x00000144
+#define DDRSS_DDRPHY_RDIMMGCR2 0x00000148
+#define DDRSS_DDRPHY_RDIMMCR0 0x00000150
+#define DDRSS_DDRPHY_RDIMMCR1 0x00000154
+#define DDRSS_DDRPHY_RDIMMCR2 0x00000158
+#define DDRSS_DDRPHY_RDIMMCR3 0x0000015C
+#define DDRSS_DDRPHY_RDIMMCR4 0x00000160
+#define DDRSS_DDRPHY_SCHCR0 0x00000168
+#define DDRSS_DDRPHY_SCHCR1 0x0000016C
+#define DDRSS_DDRPHY_MR0 0x00000180
+#define DDRSS_DDRPHY_MR1 0x00000184
+#define DDRSS_DDRPHY_MR2 0x00000188
+#define DDRSS_DDRPHY_MR3 0x0000018C
+#define DDRSS_DDRPHY_MR4 0x00000190
+#define DDRSS_DDRPHY_MR5 0x00000194
+#define DDRSS_DDRPHY_MR6 0x00000198
+#define DDRSS_DDRPHY_MR7 0x0000019C
+#define DDRSS_DDRPHY_MR11 0x000001AC
+#define DDRSS_DDRPHY_MR12 0x000001B0
+#define DDRSS_DDRPHY_MR13 0x000001B4
+#define DDRSS_DDRPHY_MR14 0x000001B8
+#define DDRSS_DDRPHY_MR22 0x000001D8
+#define DDRSS_DDRPHY_DTCR0 0x00000200
+#define DDRSS_DDRPHY_DTCR1 0x00000204
+#define DDRSS_DDRPHY_DTAR0 0x00000208
+#define DDRSS_DDRPHY_DTAR1 0x0000020C
+#define DDRSS_DDRPHY_DTAR2 0x00000210
+#define DDRSS_DDRPHY_DTDR0 0x00000218
+#define DDRSS_DDRPHY_DTDR1 0x0000021C
+#define DDRSS_DDRPHY_DTEDR0 0x00000230
+#define DDRSS_DDRPHY_DTEDR1 0x00000234
+#define DDRSS_DDRPHY_DTEDR2 0x00000238
+#define DDRSS_DDRPHY_VTDR 0x0000023C
+#define DDRSS_DDRPHY_CATR0 0x00000240
+#define DDRSS_DDRPHY_CATR1 0x00000244
+#define DDRSS_DDRPHY_PGCR8 0x00000248
+#define DDRSS_DDRPHY_DQSDR0 0x00000250
+#define DDRSS_DDRPHY_DQSDR1 0x00000254
+#define DDRSS_DDRPHY_DQSDR2 0x00000258
+#define DDRSS_DDRPHY_DCUAR 0x00000300
+#define DDRSS_DDRPHY_DCUDR 0x00000304
+#define DDRSS_DDRPHY_DCURR 0x00000308
+#define DDRSS_DDRPHY_DCULR 0x0000030C
+#define DDRSS_DDRPHY_DCUGCR 0x00000310
+#define DDRSS_DDRPHY_DCUTPR 0x00000314
+#define DDRSS_DDRPHY_DCUSR0 0x00000318
+#define DDRSS_DDRPHY_DCUSR1 0x0000031C
+#define DDRSS_DDRPHY_BISTRR 0x00000400
+#define DDRSS_DDRPHY_BISTWCR 0x00000404
+#define DDRSS_DDRPHY_BISTMSKR0 0x00000408
+#define DDRSS_DDRPHY_BISTMSKR1 0x0000040C
+#define DDRSS_DDRPHY_BISTMSKR2 0x00000410
+#define DDRSS_DDRPHY_BISTLSR 0x00000414
+#define DDRSS_DDRPHY_BISTAR0 0x00000418
+#define DDRSS_DDRPHY_BISTAR1 0x0000041C
+#define DDRSS_DDRPHY_BISTAR2 0x00000420
+#define DDRSS_DDRPHY_BISTAR3 0x00000424
+#define DDRSS_DDRPHY_BISTAR4 0x00000428
+#define DDRSS_DDRPHY_BISTUDPR 0x0000042C
+#define DDRSS_DDRPHY_BISTGSR 0x00000430
+#define DDRSS_DDRPHY_BISTWER0 0x00000434
+#define DDRSS_DDRPHY_BISTWER1 0x00000438
+#define DDRSS_DDRPHY_BISTBER0 0x0000043C
+#define DDRSS_DDRPHY_BISTBER1 0x00000440
+#define DDRSS_DDRPHY_BISTBER2 0x00000444
+#define DDRSS_DDRPHY_BISTBER3 0x00000448
+#define DDRSS_DDRPHY_BISTBER4 0x0000044C
+#define DDRSS_DDRPHY_BISTWCSR 0x00000450
+#define DDRSS_DDRPHY_BISTFWR0 0x00000454
+#define DDRSS_DDRPHY_BISTFWR1 0x00000458
+#define DDRSS_DDRPHY_BISTFWR2 0x0000045C
+#define DDRSS_DDRPHY_BISTBER5 0x00000460
+#define DDRSS_DDRPHY_RANKIDR 0x000004DC
+#define DDRSS_DDRPHY_RIOCR0 0x000004E0
+#define DDRSS_DDRPHY_RIOCR1 0x000004E4
+#define DDRSS_DDRPHY_RIOCR2 0x000004E8
+#define DDRSS_DDRPHY_RIOCR3 0x000004EC
+#define DDRSS_DDRPHY_RIOCR4 0x000004F0
+#define DDRSS_DDRPHY_RIOCR5 0x000004F4
+#define DDRSS_DDRPHY_ACIOCR0 0x00000500
+#define DDRSS_DDRPHY_ACIOCR1 0x00000504
+#define DDRSS_DDRPHY_ACIOCR2 0x00000508
+#define DDRSS_DDRPHY_ACIOCR3 0x0000050C
+#define DDRSS_DDRPHY_ACIOCR4 0x00000510
+#define DDRSS_DDRPHY_ACIOCR5 0x00000514
+#define DDRSS_DDRPHY_IOVCR0 0x00000520
+#define DDRSS_DDRPHY_IOVCR1 0x00000524
+#define DDRSS_DDRPHY_VTCR0 0x00000528
+#define DDRSS_DDRPHY_VTCR1 0x0000052C
+#define DDRSS_DDRPHY_ACBDLR0 0x00000540
+#define DDRSS_DDRPHY_ACBDLR1 0x00000544
+#define DDRSS_DDRPHY_ACBDLR2 0x00000548
+#define DDRSS_DDRPHY_ACBDLR3 0x0000054C
+#define DDRSS_DDRPHY_ACBDLR4 0x00000550
+#define DDRSS_DDRPHY_ACBDLR5 0x00000554
+#define DDRSS_DDRPHY_ACBDLR6 0x00000558
+#define DDRSS_DDRPHY_ACBDLR7 0x0000055C
+#define DDRSS_DDRPHY_ACBDLR8 0x00000560
+#define DDRSS_DDRPHY_ACBDLR9 0x00000564
+#define DDRSS_DDRPHY_ACBDLR10 0x00000568
+#define DDRSS_DDRPHY_ACBDLR11 0x0000056C
+#define DDRSS_DDRPHY_ACBDLR12 0x00000570
+#define DDRSS_DDRPHY_ACBDLR13 0x00000574
+#define DDRSS_DDRPHY_ACBDLR14 0x00000578
+#define DDRSS_DDRPHY_ACBDLR15 0x0000057C
+#define DDRSS_DDRPHY_ACBDLR16 0x00000580
+#define DDRSS_DDRPHY_ACLCDLR 0x00000584
+#define DDRSS_DDRPHY_ACMDLR0 0x000005A0
+#define DDRSS_DDRPHY_ACMDLR1 0x000005A4
+#define DDRSS_DDRPHY_ZQCR 0x00000680
+#define DDRSS_DDRPHY_ZQ0PR0 0x00000684
+#define DDRSS_DDRPHY_ZQ0PR1 0x00000688
+#define DDRSS_DDRPHY_ZQ0DR0 0x0000068C
+#define DDRSS_DDRPHY_ZQ0DR1 0x00000690
+#define DDRSS_DDRPHY_ZQ0OR0 0x00000694
+#define DDRSS_DDRPHY_ZQ0OR1 0x00000698
+#define DDRSS_DDRPHY_ZQ0SR 0x0000069C
+#define DDRSS_DDRPHY_ZQ1PR0 0x000006A4
+#define DDRSS_DDRPHY_ZQ1PR1 0x000006A8
+#define DDRSS_DDRPHY_ZQ1DR0 0x000006AC
+#define DDRSS_DDRPHY_ZQ1DR1 0x000006B0
+#define DDRSS_DDRPHY_ZQ1OR0 0x000006B4
+#define DDRSS_DDRPHY_ZQ1OR1 0x000006B8
+#define DDRSS_DDRPHY_ZQ1SR 0x000006BC
+#define DDRSS_DDRPHY_ZQ2PR0 0x000006C4
+#define DDRSS_DDRPHY_ZQ2PR1 0x000006C8
+#define DDRSS_DDRPHY_ZQ2DR0 0x000006CC
+#define DDRSS_DDRPHY_ZQ2DR1 0x000006D0
+#define DDRSS_DDRPHY_ZQ2OR0 0x000006D4
+#define DDRSS_DDRPHY_ZQ2OR1 0x000006D8
+#define DDRSS_DDRPHY_ZQ2SR 0x000006DC
+#define DDRSS_DDRPHY_ZQ3PR0 0x000006E4
+#define DDRSS_DDRPHY_ZQ3PR1 0x000006E8
+#define DDRSS_DDRPHY_ZQ3DR0 0x000006EC
+#define DDRSS_DDRPHY_ZQ3DR1 0x000006F0
+#define DDRSS_DDRPHY_ZQ3OR0 0x000006F4
+#define DDRSS_DDRPHY_ZQ3OR1 0x000006F8
+#define DDRSS_DDRPHY_ZQ3SR 0x000006FC
+#define DDRSS_DDRPHY_DX0GCR0 0x00000700
+#define DDRSS_DDRPHY_DX0GCR1 0x00000704
+#define DDRSS_DDRPHY_DX0GCR2 0x00000708
+#define DDRSS_DDRPHY_DX0GCR3 0x0000070C
+#define DDRSS_DDRPHY_DX0GCR4 0x00000710
+#define DDRSS_DDRPHY_DX0GCR5 0x00000714
+#define DDRSS_DDRPHY_DX0GCR6 0x00000718
+#define DDRSS_DDRPHY_DX0GCR7 0x0000071C
+#define DDRSS_DDRPHY_DX0GCR8 0x00000720
+#define DDRSS_DDRPHY_DX0GCR9 0x00000724
+#define DDRSS_DDRPHY_DX0DQMAP0 0x00000728
+#define DDRSS_DDRPHY_DX0DQMAP1 0x0000072C
+#define DDRSS_DDRPHY_DX0BDLR0 0x00000740
+#define DDRSS_DDRPHY_DX0BDLR1 0x00000744
+#define DDRSS_DDRPHY_DX0BDLR2 0x00000748
+#define DDRSS_DDRPHY_DX0BDLR3 0x00000750
+#define DDRSS_DDRPHY_DX0BDLR4 0x00000754
+#define DDRSS_DDRPHY_DX0BDLR5 0x00000758
+#define DDRSS_DDRPHY_DX0BDLR6 0x00000760
+#define DDRSS_DDRPHY_DX0BDLR7 0x00000764
+#define DDRSS_DDRPHY_DX0BDLR8 0x00000768
+#define DDRSS_DDRPHY_DX0BDLR9 0x0000076C
+#define DDRSS_DDRPHY_DX0LCDLR0 0x00000780
+#define DDRSS_DDRPHY_DX0LCDLR1 0x00000784
+#define DDRSS_DDRPHY_DX0LCDLR2 0x00000788
+#define DDRSS_DDRPHY_DX0LCDLR3 0x0000078C
+#define DDRSS_DDRPHY_DX0LCDLR4 0x00000790
+#define DDRSS_DDRPHY_DX0LCDLR5 0x00000794
+#define DDRSS_DDRPHY_DX0MDLR0 0x000007A0
+#define DDRSS_DDRPHY_DX0MDLR1 0x000007A4
+#define DDRSS_DDRPHY_DX0GTR0 0x000007C0
+#define DDRSS_DDRPHY_DX0RSR0 0x000007D0
+#define DDRSS_DDRPHY_DX0RSR1 0x000007D4
+#define DDRSS_DDRPHY_DX0RSR2 0x000007D8
+#define DDRSS_DDRPHY_DX0RSR3 0x000007DC
+#define DDRSS_DDRPHY_DX0GSR0 0x000007E0
+#define DDRSS_DDRPHY_DX0GSR1 0x000007E4
+#define DDRSS_DDRPHY_DX0GSR2 0x000007E8
+#define DDRSS_DDRPHY_DX0GSR3 0x000007EC
+#define DDRSS_DDRPHY_DX0GSR4 0x000007F0
+#define DDRSS_DDRPHY_DX0GSR5 0x000007F4
+#define DDRSS_DDRPHY_DX0GSR6 0x000007F8
+#define DDRSS_DDRPHY_DX1GCR0 0x00000800
+#define DDRSS_DDRPHY_DX1GCR1 0x00000804
+#define DDRSS_DDRPHY_DX1GCR2 0x00000808
+#define DDRSS_DDRPHY_DX1GCR3 0x0000080C
+#define DDRSS_DDRPHY_DX1GCR4 0x00000810
+#define DDRSS_DDRPHY_DX1GCR5 0x00000814
+#define DDRSS_DDRPHY_DX1GCR6 0x00000818
+#define DDRSS_DDRPHY_DX1GCR7 0x0000081C
+#define DDRSS_DDRPHY_DX1GCR8 0x00000820
+#define DDRSS_DDRPHY_DX1GCR9 0x00000824
+#define DDRSS_DDRPHY_DX1DQMAP0 0x00000828
+#define DDRSS_DDRPHY_DX1DQMAP1 0x0000082C
+#define DDRSS_DDRPHY_DX1BDLR0 0x00000840
+#define DDRSS_DDRPHY_DX1BDLR1 0x00000844
+#define DDRSS_DDRPHY_DX1BDLR2 0x00000848
+#define DDRSS_DDRPHY_DX1BDLR3 0x00000850
+#define DDRSS_DDRPHY_DX1BDLR4 0x00000854
+#define DDRSS_DDRPHY_DX1BDLR5 0x00000858
+#define DDRSS_DDRPHY_DX1BDLR6 0x00000860
+#define DDRSS_DDRPHY_DX1BDLR7 0x00000864
+#define DDRSS_DDRPHY_DX1BDLR8 0x00000868
+#define DDRSS_DDRPHY_DX1BDLR9 0x0000086C
+#define DDRSS_DDRPHY_DX1LCDLR0 0x00000880
+#define DDRSS_DDRPHY_DX1LCDLR1 0x00000884
+#define DDRSS_DDRPHY_DX1LCDLR2 0x00000888
+#define DDRSS_DDRPHY_DX1LCDLR3 0x0000088C
+#define DDRSS_DDRPHY_DX1LCDLR4 0x00000890
+#define DDRSS_DDRPHY_DX1LCDLR5 0x00000894
+#define DDRSS_DDRPHY_DX1MDLR0 0x000008A0
+#define DDRSS_DDRPHY_DX1MDLR1 0x000008A4
+#define DDRSS_DDRPHY_DX1GTR0 0x000008C0
+#define DDRSS_DDRPHY_DX1RSR0 0x000008D0
+#define DDRSS_DDRPHY_DX1RSR1 0x000008D4
+#define DDRSS_DDRPHY_DX1RSR2 0x000008D8
+#define DDRSS_DDRPHY_DX1RSR3 0x000008DC
+#define DDRSS_DDRPHY_DX1GSR0 0x000008E0
+#define DDRSS_DDRPHY_DX1GSR1 0x000008E4
+#define DDRSS_DDRPHY_DX1GSR2 0x000008E8
+#define DDRSS_DDRPHY_DX1GSR3 0x000008EC
+#define DDRSS_DDRPHY_DX1GSR4 0x000008F0
+#define DDRSS_DDRPHY_DX1GSR5 0x000008F4
+#define DDRSS_DDRPHY_DX1GSR6 0x000008F8
+#define DDRSS_DDRPHY_DX2GCR0 0x00000900
+#define DDRSS_DDRPHY_DX2GCR1 0x00000904
+#define DDRSS_DDRPHY_DX2GCR2 0x00000908
+#define DDRSS_DDRPHY_DX2GCR3 0x0000090C
+#define DDRSS_DDRPHY_DX2GCR4 0x00000910
+#define DDRSS_DDRPHY_DX2GCR5 0x00000914
+#define DDRSS_DDRPHY_DX2GCR6 0x00000918
+#define DDRSS_DDRPHY_DX2GCR7 0x0000091C
+#define DDRSS_DDRPHY_DX2GCR8 0x00000920
+#define DDRSS_DDRPHY_DX2GCR9 0x00000924
+#define DDRSS_DDRPHY_DX2DQMAP0 0x00000928
+#define DDRSS_DDRPHY_DX2DQMAP1 0x0000092C
+#define DDRSS_DDRPHY_DX2BDLR0 0x00000940
+#define DDRSS_DDRPHY_DX2BDLR1 0x00000944
+#define DDRSS_DDRPHY_DX2BDLR2 0x00000948
+#define DDRSS_DDRPHY_DX2BDLR3 0x00000950
+#define DDRSS_DDRPHY_DX2BDLR4 0x00000954
+#define DDRSS_DDRPHY_DX2BDLR5 0x00000958
+#define DDRSS_DDRPHY_DX2BDLR6 0x00000960
+#define DDRSS_DDRPHY_DX2BDLR7 0x00000964
+#define DDRSS_DDRPHY_DX2BDLR8 0x00000968
+#define DDRSS_DDRPHY_DX2BDLR9 0x0000096C
+#define DDRSS_DDRPHY_DX2LCDLR0 0x00000980
+#define DDRSS_DDRPHY_DX2LCDLR1 0x00000984
+#define DDRSS_DDRPHY_DX2LCDLR2 0x00000988
+#define DDRSS_DDRPHY_DX2LCDLR3 0x0000098C
+#define DDRSS_DDRPHY_DX2LCDLR4 0x00000990
+#define DDRSS_DDRPHY_DX2LCDLR5 0x00000994
+#define DDRSS_DDRPHY_DX2MDLR0 0x000009A0
+#define DDRSS_DDRPHY_DX2MDLR1 0x000009A4
+#define DDRSS_DDRPHY_DX2GTR0 0x000009C0
+#define DDRSS_DDRPHY_DX2RSR0 0x000009D0
+#define DDRSS_DDRPHY_DX2RSR1 0x000009D4
+#define DDRSS_DDRPHY_DX2RSR2 0x000009D8
+#define DDRSS_DDRPHY_DX2RSR3 0x000009DC
+#define DDRSS_DDRPHY_DX2GSR0 0x000009E0
+#define DDRSS_DDRPHY_DX2GSR1 0x000009E4
+#define DDRSS_DDRPHY_DX2GSR2 0x000009E8
+#define DDRSS_DDRPHY_DX2GSR3 0x000009EC
+#define DDRSS_DDRPHY_DX2GSR4 0x000009F0
+#define DDRSS_DDRPHY_DX2GSR5 0x000009F4
+#define DDRSS_DDRPHY_DX2GSR6 0x000009F8
+#define DDRSS_DDRPHY_DX3GCR0 0x00000A00
+#define DDRSS_DDRPHY_DX3GCR1 0x00000A04
+#define DDRSS_DDRPHY_DX3GCR2 0x00000A08
+#define DDRSS_DDRPHY_DX3GCR3 0x00000A0C
+#define DDRSS_DDRPHY_DX3GCR4 0x00000A10
+#define DDRSS_DDRPHY_DX3GCR5 0x00000A14
+#define DDRSS_DDRPHY_DX3GCR6 0x00000A18
+#define DDRSS_DDRPHY_DX3GCR7 0x00000A1C
+#define DDRSS_DDRPHY_DX3GCR8 0x00000A20
+#define DDRSS_DDRPHY_DX3GCR9 0x00000A24
+#define DDRSS_DDRPHY_DX3DQMAP0 0x00000A28
+#define DDRSS_DDRPHY_DX3DQMAP1 0x00000A2C
+#define DDRSS_DDRPHY_DX3BDLR0 0x00000A40
+#define DDRSS_DDRPHY_DX3BDLR1 0x00000A44
+#define DDRSS_DDRPHY_DX3BDLR2 0x00000A48
+#define DDRSS_DDRPHY_DX3BDLR3 0x00000A50
+#define DDRSS_DDRPHY_DX3BDLR4 0x00000A54
+#define DDRSS_DDRPHY_DX3BDLR5 0x00000A58
+#define DDRSS_DDRPHY_DX3BDLR6 0x00000A60
+#define DDRSS_DDRPHY_DX3BDLR7 0x00000A64
+#define DDRSS_DDRPHY_DX3BDLR8 0x00000A68
+#define DDRSS_DDRPHY_DX3BDLR9 0x00000A6C
+#define DDRSS_DDRPHY_DX3LCDLR0 0x00000A80
+#define DDRSS_DDRPHY_DX3LCDLR1 0x00000A84
+#define DDRSS_DDRPHY_DX3LCDLR2 0x00000A88
+#define DDRSS_DDRPHY_DX3LCDLR3 0x00000A8C
+#define DDRSS_DDRPHY_DX3LCDLR4 0x00000A90
+#define DDRSS_DDRPHY_DX3LCDLR5 0x00000A94
+#define DDRSS_DDRPHY_DX3MDLR0 0x00000AA0
+#define DDRSS_DDRPHY_DX3MDLR1 0x00000AA4
+#define DDRSS_DDRPHY_DX3GTR0 0x00000AC0
+#define DDRSS_DDRPHY_DX3RSR0 0x00000AD0
+#define DDRSS_DDRPHY_DX3RSR1 0x00000AD4
+#define DDRSS_DDRPHY_DX3RSR2 0x00000AD8
+#define DDRSS_DDRPHY_DX3RSR3 0x00000ADC
+#define DDRSS_DDRPHY_DX3GSR0 0x00000AE0
+#define DDRSS_DDRPHY_DX3GSR1 0x00000AE4
+#define DDRSS_DDRPHY_DX3GSR2 0x00000AE8
+#define DDRSS_DDRPHY_DX3GSR3 0x00000AEC
+#define DDRSS_DDRPHY_DX3GSR4 0x00000AF0
+#define DDRSS_DDRPHY_DX3GSR5 0x00000AF4
+#define DDRSS_DDRPHY_DX3GSR6 0x00000AF8
+#define DDRSS_DDRPHY_DX4GCR0 0x00000B00
+#define DDRSS_DDRPHY_DX4GCR1 0x00000B04
+#define DDRSS_DDRPHY_DX4GCR2 0x00000B08
+#define DDRSS_DDRPHY_DX4GCR3 0x00000B0C
+#define DDRSS_DDRPHY_DX4GCR4 0x00000B10
+#define DDRSS_DDRPHY_DX4GCR5 0x00000B14
+#define DDRSS_DDRPHY_DX4GCR6 0x00000B18
+#define DDRSS_DDRPHY_DX4GCR7 0x00000B1C
+#define DDRSS_DDRPHY_DX4GCR8 0x00000B20
+#define DDRSS_DDRPHY_DX4GCR9 0x00000B24
+#define DDRSS_DDRPHY_DX4DQMAP0 0x00000B28
+#define DDRSS_DDRPHY_DX4DQMAP1 0x00000B2C
+#define DDRSS_DDRPHY_DX4BDLR0 0x00000B40
+#define DDRSS_DDRPHY_DX4BDLR1 0x00000B44
+#define DDRSS_DDRPHY_DX4BDLR2 0x00000B48
+#define DDRSS_DDRPHY_DX4BDLR3 0x00000B50
+#define DDRSS_DDRPHY_DX4BDLR4 0x00000B54
+#define DDRSS_DDRPHY_DX4BDLR5 0x00000B58
+#define DDRSS_DDRPHY_DX4BDLR6 0x00000B60
+#define DDRSS_DDRPHY_DX4BDLR7 0x00000B64
+#define DDRSS_DDRPHY_DX4BDLR8 0x00000B68
+#define DDRSS_DDRPHY_DX4BDLR9 0x00000B6C
+#define DDRSS_DDRPHY_DX4LCDLR0 0x00000B80
+#define DDRSS_DDRPHY_DX4LCDLR1 0x00000B84
+#define DDRSS_DDRPHY_DX4LCDLR2 0x00000B88
+#define DDRSS_DDRPHY_DX4LCDLR3 0x00000B8C
+#define DDRSS_DDRPHY_DX4LCDLR4 0x00000B90
+#define DDRSS_DDRPHY_DX4LCDLR5 0x00000B94
+#define DDRSS_DDRPHY_DX4MDLR0 0x00000BA0
+#define DDRSS_DDRPHY_DX4MDLR1 0x00000BA4
+#define DDRSS_DDRPHY_DX4GTR0 0x00000BC0
+#define DDRSS_DDRPHY_DX4RSR0 0x00000BD0
+#define DDRSS_DDRPHY_DX4RSR1 0x00000BD4
+#define DDRSS_DDRPHY_DX4RSR2 0x00000BD8
+#define DDRSS_DDRPHY_DX4RSR3 0x00000BDC
+#define DDRSS_DDRPHY_DX4GSR0 0x00000BE0
+#define DDRSS_DDRPHY_DX4GSR1 0x00000BE4
+#define DDRSS_DDRPHY_DX4GSR2 0x00000BE8
+#define DDRSS_DDRPHY_DX4GSR3 0x00000BEC
+#define DDRSS_DDRPHY_DX4GSR4 0x00000BF0
+#define DDRSS_DDRPHY_DX4GSR5 0x00000BF4
+#define DDRSS_DDRPHY_DX4GSR6 0x00000BF8
+#define DDRSS_DDRPHY_DX5GCR0 0x00000C00
+#define DDRSS_DDRPHY_DX5GCR1 0x00000C04
+#define DDRSS_DDRPHY_DX5GCR2 0x00000C08
+#define DDRSS_DDRPHY_DX5GCR3 0x00000C0C
+#define DDRSS_DDRPHY_DX5GCR4 0x00000C10
+#define DDRSS_DDRPHY_DX5GCR5 0x00000C14
+#define DDRSS_DDRPHY_DX5GCR6 0x00000C18
+#define DDRSS_DDRPHY_DX5GCR7 0x00000C1C
+#define DDRSS_DDRPHY_DX5GCR8 0x00000C20
+#define DDRSS_DDRPHY_DX5GCR9 0x00000C24
+#define DDRSS_DDRPHY_DX5DQMAP0 0x00000C28
+#define DDRSS_DDRPHY_DX5DQMAP1 0x00000C2C
+#define DDRSS_DDRPHY_DX5BDLR0 0x00000C40
+#define DDRSS_DDRPHY_DX5BDLR1 0x00000C44
+#define DDRSS_DDRPHY_DX5BDLR2 0x00000C48
+#define DDRSS_DDRPHY_DX5BDLR3 0x00000C50
+#define DDRSS_DDRPHY_DX5BDLR4 0x00000C54
+#define DDRSS_DDRPHY_DX5BDLR5 0x00000C58
+#define DDRSS_DDRPHY_DX5BDLR6 0x00000C60
+#define DDRSS_DDRPHY_DX5BDLR7 0x00000C64
+#define DDRSS_DDRPHY_DX5BDLR8 0x00000C68
+#define DDRSS_DDRPHY_DX5BDLR9 0x00000C6C
+#define DDRSS_DDRPHY_DX5LCDLR0 0x00000C80
+#define DDRSS_DDRPHY_DX5LCDLR1 0x00000C84
+#define DDRSS_DDRPHY_DX5LCDLR2 0x00000C88
+#define DDRSS_DDRPHY_DX5LCDLR3 0x00000C8C
+#define DDRSS_DDRPHY_DX5LCDLR4 0x00000C90
+#define DDRSS_DDRPHY_DX5LCDLR5 0x00000C94
+#define DDRSS_DDRPHY_DX5MDLR0 0x00000CA0
+#define DDRSS_DDRPHY_DX5MDLR1 0x00000CA4
+#define DDRSS_DDRPHY_DX5GTR0 0x00000CC0
+#define DDRSS_DDRPHY_DX5RSR0 0x00000CD0
+#define DDRSS_DDRPHY_DX5RSR1 0x00000CD4
+#define DDRSS_DDRPHY_DX5RSR2 0x00000CD8
+#define DDRSS_DDRPHY_DX5RSR3 0x00000CDC
+#define DDRSS_DDRPHY_DX5GSR0 0x00000CE0
+#define DDRSS_DDRPHY_DX5GSR1 0x00000CE4
+#define DDRSS_DDRPHY_DX5GSR2 0x00000CE8
+#define DDRSS_DDRPHY_DX5GSR3 0x00000CEC
+#define DDRSS_DDRPHY_DX5GSR4 0x00000CF0
+#define DDRSS_DDRPHY_DX5GSR5 0x00000CF4
+#define DDRSS_DDRPHY_DX5GSR6 0x00000CF8
+#define DDRSS_DDRPHY_DX6GCR0 0x00000D00
+#define DDRSS_DDRPHY_DX6GCR1 0x00000D04
+#define DDRSS_DDRPHY_DX6GCR2 0x00000D08
+#define DDRSS_DDRPHY_DX6GCR3 0x00000D0C
+#define DDRSS_DDRPHY_DX6GCR4 0x00000D10
+#define DDRSS_DDRPHY_DX6GCR5 0x00000D14
+#define DDRSS_DDRPHY_DX6GCR6 0x00000D18
+#define DDRSS_DDRPHY_DX6GCR7 0x00000D1C
+#define DDRSS_DDRPHY_DX6GCR8 0x00000D20
+#define DDRSS_DDRPHY_DX6GCR9 0x00000D24
+#define DDRSS_DDRPHY_DX6DQMAP0 0x00000D28
+#define DDRSS_DDRPHY_DX6DQMAP1 0x00000D2C
+#define DDRSS_DDRPHY_DX6BDLR0 0x00000D40
+#define DDRSS_DDRPHY_DX6BDLR1 0x00000D44
+#define DDRSS_DDRPHY_DX6BDLR2 0x00000D48
+#define DDRSS_DDRPHY_DX6BDLR3 0x00000D50
+#define DDRSS_DDRPHY_DX6BDLR4 0x00000D54
+#define DDRSS_DDRPHY_DX6BDLR5 0x00000D58
+#define DDRSS_DDRPHY_DX6BDLR6 0x00000D60
+#define DDRSS_DDRPHY_DX6BDLR7 0x00000D64
+#define DDRSS_DDRPHY_DX6BDLR8 0x00000D68
+#define DDRSS_DDRPHY_DX6BDLR9 0x00000D6C
+#define DDRSS_DDRPHY_DX6LCDLR0 0x00000D80
+#define DDRSS_DDRPHY_DX6LCDLR1 0x00000D84
+#define DDRSS_DDRPHY_DX6LCDLR2 0x00000D88
+#define DDRSS_DDRPHY_DX6LCDLR3 0x00000D8C
+#define DDRSS_DDRPHY_DX6LCDLR4 0x00000D90
+#define DDRSS_DDRPHY_DX6LCDLR5 0x00000D94
+#define DDRSS_DDRPHY_DX6MDLR0 0x00000DA0
+#define DDRSS_DDRPHY_DX6MDLR1 0x00000DA4
+#define DDRSS_DDRPHY_DX6GTR0 0x00000DC0
+#define DDRSS_DDRPHY_DX6RSR0 0x00000DD0
+#define DDRSS_DDRPHY_DX6RSR1 0x00000DD4
+#define DDRSS_DDRPHY_DX6RSR2 0x00000DD8
+#define DDRSS_DDRPHY_DX6RSR3 0x00000DDC
+#define DDRSS_DDRPHY_DX6GSR0 0x00000DE0
+#define DDRSS_DDRPHY_DX6GSR1 0x00000DE4
+#define DDRSS_DDRPHY_DX6GSR2 0x00000DE8
+#define DDRSS_DDRPHY_DX6GSR3 0x00000DEC
+#define DDRSS_DDRPHY_DX6GSR4 0x00000DF0
+#define DDRSS_DDRPHY_DX6GSR5 0x00000DF4
+#define DDRSS_DDRPHY_DX6GSR6 0x00000DF8
+#define DDRSS_DDRPHY_DX7GCR0 0x00000E00
+#define DDRSS_DDRPHY_DX7GCR1 0x00000E04
+#define DDRSS_DDRPHY_DX7GCR2 0x00000E08
+#define DDRSS_DDRPHY_DX7GCR3 0x00000E0C
+#define DDRSS_DDRPHY_DX7GCR4 0x00000E10
+#define DDRSS_DDRPHY_DX7GCR5 0x00000E14
+#define DDRSS_DDRPHY_DX7GCR6 0x00000E18
+#define DDRSS_DDRPHY_DX7GCR7 0x00000E1C
+#define DDRSS_DDRPHY_DX7GCR8 0x00000E20
+#define DDRSS_DDRPHY_DX7GCR9 0x00000E24
+#define DDRSS_DDRPHY_DX7DQMAP0 0x00000E28
+#define DDRSS_DDRPHY_DX7DQMAP1 0x00000E2C
+#define DDRSS_DDRPHY_DX7BDLR0 0x00000E40
+#define DDRSS_DDRPHY_DX7BDLR1 0x00000E44
+#define DDRSS_DDRPHY_DX7BDLR2 0x00000E48
+#define DDRSS_DDRPHY_DX7BDLR3 0x00000E50
+#define DDRSS_DDRPHY_DX7BDLR4 0x00000E54
+#define DDRSS_DDRPHY_DX7BDLR5 0x00000E58
+#define DDRSS_DDRPHY_DX7BDLR6 0x00000E60
+#define DDRSS_DDRPHY_DX7BDLR7 0x00000E64
+#define DDRSS_DDRPHY_DX7BDLR8 0x00000E68
+#define DDRSS_DDRPHY_DX7BDLR9 0x00000E6C
+#define DDRSS_DDRPHY_DX7LCDLR0 0x00000E80
+#define DDRSS_DDRPHY_DX7LCDLR1 0x00000E84
+#define DDRSS_DDRPHY_DX7LCDLR2 0x00000E88
+#define DDRSS_DDRPHY_DX7LCDLR3 0x00000E8C
+#define DDRSS_DDRPHY_DX7LCDLR4 0x00000E90
+#define DDRSS_DDRPHY_DX7LCDLR5 0x00000E94
+#define DDRSS_DDRPHY_DX7MDLR0 0x00000EA0
+#define DDRSS_DDRPHY_DX7MDLR1 0x00000EA4
+#define DDRSS_DDRPHY_DX7GTR0 0x00000EC0
+#define DDRSS_DDRPHY_DX7RSR0 0x00000ED0
+#define DDRSS_DDRPHY_DX7RSR1 0x00000ED4
+#define DDRSS_DDRPHY_DX7RSR2 0x00000ED8
+#define DDRSS_DDRPHY_DX7RSR3 0x00000EDC
+#define DDRSS_DDRPHY_DX7GSR0 0x00000EE0
+#define DDRSS_DDRPHY_DX7GSR1 0x00000EE4
+#define DDRSS_DDRPHY_DX7GSR2 0x00000EE8
+#define DDRSS_DDRPHY_DX7GSR3 0x00000EEC
+#define DDRSS_DDRPHY_DX7GSR4 0x00000EF0
+#define DDRSS_DDRPHY_DX7GSR5 0x00000EF4
+#define DDRSS_DDRPHY_DX7GSR6 0x00000EF8
+#define DDRSS_DDRPHY_DX8GCR0 0x00000F00
+#define DDRSS_DDRPHY_DX8GCR1 0x00000F04
+#define DDRSS_DDRPHY_DX8GCR2 0x00000F08
+#define DDRSS_DDRPHY_DX8GCR3 0x00000F0C
+#define DDRSS_DDRPHY_DX8GCR4 0x00000F10
+#define DDRSS_DDRPHY_DX8GCR5 0x00000F14
+#define DDRSS_DDRPHY_DX8GCR6 0x00000F18
+#define DDRSS_DDRPHY_DX8GCR7 0x00000F1C
+#define DDRSS_DDRPHY_DX8GCR8 0x00000F20
+#define DDRSS_DDRPHY_DX8GCR9 0x00000F24
+#define DDRSS_DDRPHY_DX8DQMAP0 0x00000F28
+#define DDRSS_DDRPHY_DX8DQMAP1 0x00000F2C
+#define DDRSS_DDRPHY_DX8BDLR0 0x00000F40
+#define DDRSS_DDRPHY_DX8BDLR1 0x00000F44
+#define DDRSS_DDRPHY_DX8BDLR2 0x00000F48
+#define DDRSS_DDRPHY_DX8BDLR3 0x00000F50
+#define DDRSS_DDRPHY_DX8BDLR4 0x00000F54
+#define DDRSS_DDRPHY_DX8BDLR5 0x00000F58
+#define DDRSS_DDRPHY_DX8BDLR6 0x00000F60
+#define DDRSS_DDRPHY_DX8BDLR7 0x00000F64
+#define DDRSS_DDRPHY_DX8BDLR8 0x00000F68
+#define DDRSS_DDRPHY_DX8BDLR9 0x00000F6C
+#define DDRSS_DDRPHY_DX8LCDLR0 0x00000F80
+#define DDRSS_DDRPHY_DX8LCDLR1 0x00000F84
+#define DDRSS_DDRPHY_DX8LCDLR2 0x00000F88
+#define DDRSS_DDRPHY_DX8LCDLR3 0x00000F8C
+#define DDRSS_DDRPHY_DX8LCDLR4 0x00000F90
+#define DDRSS_DDRPHY_DX8LCDLR5 0x00000F94
+#define DDRSS_DDRPHY_DX8MDLR0 0x00000FA0
+#define DDRSS_DDRPHY_DX8MDLR1 0x00000FA4
+#define DDRSS_DDRPHY_DX8GTR0 0x00000FC0
+#define DDRSS_DDRPHY_DX8RSR0 0x00000FD0
+#define DDRSS_DDRPHY_DX8RSR1 0x00000FD4
+#define DDRSS_DDRPHY_DX8RSR2 0x00000FD8
+#define DDRSS_DDRPHY_DX8RSR3 0x00000FDC
+#define DDRSS_DDRPHY_DX8GSR0 0x00000FE0
+#define DDRSS_DDRPHY_DX8GSR1 0x00000FE4
+#define DDRSS_DDRPHY_DX8GSR2 0x00000FE8
+#define DDRSS_DDRPHY_DX8GSR3 0x00000FEC
+#define DDRSS_DDRPHY_DX8GSR4 0x00000FF0
+#define DDRSS_DDRPHY_DX8GSR5 0x00000FF4
+#define DDRSS_DDRPHY_DX8GSR6 0x00000FF8
+#define DDRSS_DDRPHY_DX8SL0OSC 0x00001400
+#define DDRSS_DDRPHY_DX8SL0PLLCR0 0x00001404
+#define DDRSS_DDRPHY_DX8SL0PLLCR1 0x00001408
+#define DDRSS_DDRPHY_DX8SL0PLLCR2 0x0000140C
+#define DDRSS_DDRPHY_DX8SL0PLLCR3 0x00001410
+#define DDRSS_DDRPHY_DX8SL0PLLCR4 0x00001414
+#define DDRSS_DDRPHY_DX8SL0PLLCR5 0x00001418
+#define DDRSS_DDRPHY_DX8SL0DQSCTL 0x0000141C
+#define DDRSS_DDRPHY_DX8SL0TRNCTL 0x00001420
+#define DDRSS_DDRPHY_DX8SL0DDLCTL 0x00001424
+#define DDRSS_DDRPHY_DX8SL0DXCTL1 0x00001428
+#define DDRSS_DDRPHY_DX8SL0DXCTL2 0x0000142C
+#define DDRSS_DDRPHY_DX8SL0IOCR 0x00001430
+#define DDRSS_DDRPHY_DX4SL0IOCR 0x00001434
+#define DDRSS_DDRPHY_DX8SL1OSC 0x00001440
+#define DDRSS_DDRPHY_DX8SL1PLLCR0 0x00001444
+#define DDRSS_DDRPHY_DX8SL1PLLCR1 0x00001448
+#define DDRSS_DDRPHY_DX8SL1PLLCR2 0x0000144C
+#define DDRSS_DDRPHY_DX8SL1PLLCR3 0x00001450
+#define DDRSS_DDRPHY_DX8SL1PLLCR4 0x00001454
+#define DDRSS_DDRPHY_DX8SL1PLLCR5 0x00001458
+#define DDRSS_DDRPHY_DX8SL1DQSCTL 0x0000145C
+#define DDRSS_DDRPHY_DX8SL1TRNCTL 0x00001460
+#define DDRSS_DDRPHY_DX8SL1DDLCTL 0x00001464
+#define DDRSS_DDRPHY_DX8SL1DXCTL1 0x00001468
+#define DDRSS_DDRPHY_DX8SL1DXCTL2 0x0000146C
+#define DDRSS_DDRPHY_DX8SL1IOCR 0x00001470
+#define DDRSS_DDRPHY_DX4SL1IOCR 0x00001474
+#define DDRSS_DDRPHY_DX8SL2OSC 0x00001480
+#define DDRSS_DDRPHY_DX8SL2PLLCR0 0x00001484
+#define DDRSS_DDRPHY_DX8SL2PLLCR1 0x00001488
+#define DDRSS_DDRPHY_DX8SL2PLLCR2 0x0000148C
+#define DDRSS_DDRPHY_DX8SL2PLLCR3 0x00001490
+#define DDRSS_DDRPHY_DX8SL2PLLCR4 0x00001494
+#define DDRSS_DDRPHY_DX8SL2PLLCR5 0x00001498
+#define DDRSS_DDRPHY_DX8SL2DQSCTL 0x0000149C
+#define DDRSS_DDRPHY_DX8SL2TRNCTL 0x000014A0
+#define DDRSS_DDRPHY_DX8SL2DDLCTL 0x000014A4
+#define DDRSS_DDRPHY_DX8SL2DXCTL1 0x000014A8
+#define DDRSS_DDRPHY_DX8SL2DXCTL2 0x000014AC
+#define DDRSS_DDRPHY_DX8SL2IOCR 0x000014B0
+#define DDRSS_DDRPHY_DX4SL2IOCR 0x000014B4
+#define DDRSS_DDRPHY_DX8SL3OSC 0x000014C0
+#define DDRSS_DDRPHY_DX8SL3PLLCR0 0x000014C4
+#define DDRSS_DDRPHY_DX8SL3PLLCR1 0x000014C8
+#define DDRSS_DDRPHY_DX8SL3PLLCR2 0x000014CC
+#define DDRSS_DDRPHY_DX8SL3PLLCR3 0x000014D0
+#define DDRSS_DDRPHY_DX8SL3PLLCR4 0x000014D4
+#define DDRSS_DDRPHY_DX8SL3PLLCR5 0x000014D8
+#define DDRSS_DDRPHY_DX8SL3DQSCTL 0x000014DC
+#define DDRSS_DDRPHY_DX8SL3TRNCTL 0x000014E0
+#define DDRSS_DDRPHY_DX8SL3DDLCTL 0x000014E4
+#define DDRSS_DDRPHY_DX8SL3DXCTL1 0x000014E8
+#define DDRSS_DDRPHY_DX8SL3DXCTL2 0x000014EC
+#define DDRSS_DDRPHY_DX8SL3IOCR 0x000014F0
+#define DDRSS_DDRPHY_DX4SL3IOCR 0x000014F4
+#define DDRSS_DDRPHY_DX8SL4OSC 0x00001500
+#define DDRSS_DDRPHY_DX8SL4PLLCR0 0x00001504
+#define DDRSS_DDRPHY_DX8SL4PLLCR1 0x00001508
+#define DDRSS_DDRPHY_DX8SL4PLLCR2 0x0000150C
+#define DDRSS_DDRPHY_DX8SL4PLLCR3 0x00001510
+#define DDRSS_DDRPHY_DX8SL4PLLCR4 0x00001514
+#define DDRSS_DDRPHY_DX8SL4PLLCR5 0x00001518
+#define DDRSS_DDRPHY_DX8SL4DQSCTL 0x0000151C
+#define DDRSS_DDRPHY_DX8SL4TRNCTL 0x00001520
+#define DDRSS_DDRPHY_DX8SL4DDLCTL 0x00001524
+#define DDRSS_DDRPHY_DX8SL4DXCTL1 0x00001528
+#define DDRSS_DDRPHY_DX8SL4DXCTL2 0x0000152C
+#define DDRSS_DDRPHY_DX8SL4IOCR 0x00001530
+#define DDRSS_DDRPHY_DX4SL4IOCR 0x00001534
+#define DDRSS_DDRPHY_DX8SL5OSC 0x00001540
+#define DDRSS_DDRPHY_DX8SL5PLLCR0 0x00001544
+#define DDRSS_DDRPHY_DX8SL5PLLCR1 0x00001548
+#define DDRSS_DDRPHY_DX8SL5PLLCR2 0x0000154C
+#define DDRSS_DDRPHY_DX8SL5PLLCR3 0x00001550
+#define DDRSS_DDRPHY_DX8SL5PLLCR4 0x00001554
+#define DDRSS_DDRPHY_DX8SL5PLLCR5 0x00001558
+#define DDRSS_DDRPHY_DX8SL5DQSCTL 0x0000155C
+#define DDRSS_DDRPHY_DX8SL5TRNCTL 0x00001560
+#define DDRSS_DDRPHY_DX8SL5DDLCTL 0x00001564
+#define DDRSS_DDRPHY_DX8SL5DXCTL1 0x00001568
+#define DDRSS_DDRPHY_DX8SL5DXCTL2 0x0000156C
+#define DDRSS_DDRPHY_DX8SL5IOCR 0x00001570
+#define DDRSS_DDRPHY_DX4SL5IOCR 0x00001574
+#define DDRSS_DDRPHY_DX8SL6OSC 0x00001580
+#define DDRSS_DDRPHY_DX8SL6PLLCR0 0x00001584
+#define DDRSS_DDRPHY_DX8SL6PLLCR1 0x00001588
+#define DDRSS_DDRPHY_DX8SL6PLLCR2 0x0000158C
+#define DDRSS_DDRPHY_DX8SL6PLLCR3 0x00001590
+#define DDRSS_DDRPHY_DX8SL6PLLCR4 0x00001594
+#define DDRSS_DDRPHY_DX8SL6PLLCR5 0x00001598
+#define DDRSS_DDRPHY_DX8SL6DQSCTL 0x0000159C
+#define DDRSS_DDRPHY_DX8SL6TRNCTL 0x000015A0
+#define DDRSS_DDRPHY_DX8SL6DDLCTL 0x000015A4
+#define DDRSS_DDRPHY_DX8SL6DXCTL1 0x000015A8
+#define DDRSS_DDRPHY_DX8SL6DXCTL2 0x000015AC
+#define DDRSS_DDRPHY_DX8SL6IOCR 0x000015B0
+#define DDRSS_DDRPHY_DX4SL6IOCR 0x000015B4
+#define DDRSS_DDRPHY_DX8SL7OSC 0x000015C0
+#define DDRSS_DDRPHY_DX8SL7PLLCR0 0x000015C4
+#define DDRSS_DDRPHY_DX8SL7PLLCR1 0x000015C8
+#define DDRSS_DDRPHY_DX8SL7PLLCR2 0x000015CC
+#define DDRSS_DDRPHY_DX8SL7PLLCR3 0x000015D0
+#define DDRSS_DDRPHY_DX8SL7PLLCR4 0x000015D4
+#define DDRSS_DDRPHY_DX8SL7PLLCR5 0x000015D8
+#define DDRSS_DDRPHY_DX8SL7DQSCTL 0x000015DC
+#define DDRSS_DDRPHY_DX8SL7TRNCTL 0x000015E0
+#define DDRSS_DDRPHY_DX8SL7DDLCTL 0x000015E4
+#define DDRSS_DDRPHY_DX8SL7DXCTL1 0x000015E8
+#define DDRSS_DDRPHY_DX8SL7DXCTL2 0x000015EC
+#define DDRSS_DDRPHY_DX8SL7IOCR 0x000015F0
+#define DDRSS_DDRPHY_DX4SL7IOCR 0x000015F4
+#define DDRSS_DDRPHY_DX8SL8OSC 0x00001600
+#define DDRSS_DDRPHY_DX8SL8PLLCR0 0x00001604
+#define DDRSS_DDRPHY_DX8SL8PLLCR1 0x00001608
+#define DDRSS_DDRPHY_DX8SL8PLLCR2 0x0000160C
+#define DDRSS_DDRPHY_DX8SL8PLLCR3 0x00001610
+#define DDRSS_DDRPHY_DX8SL8PLLCR4 0x00001614
+#define DDRSS_DDRPHY_DX8SL8PLLCR5 0x00001618
+#define DDRSS_DDRPHY_DX8SL8DQSCTL 0x0000161C
+#define DDRSS_DDRPHY_DX8SL8TRNCTL 0x00001620
+#define DDRSS_DDRPHY_DX8SL8DDLCTL 0x00001624
+#define DDRSS_DDRPHY_DX8SL8DXCTL1 0x00001628
+#define DDRSS_DDRPHY_DX8SL8DXCTL2 0x0000162C
+#define DDRSS_DDRPHY_DX8SL8IOCR 0x00001630
+#define DDRSS_DDRPHY_DX4SL8IOCR 0x00001634
+#define DDRSS_DDRPHY_DX8SLBOSC 0x000017C0
+#define DDRSS_DDRPHY_DX8SLBPLLCR0 0x000017C4
+#define DDRSS_DDRPHY_DX8SLBPLLCR1 0x000017C8
+#define DDRSS_DDRPHY_DX8SLBPLLCR2 0x000017CC
+#define DDRSS_DDRPHY_DX8SLBPLLCR3 0x000017D0
+#define DDRSS_DDRPHY_DX8SLBPLLCR4 0x000017D4
+#define DDRSS_DDRPHY_DX8SLBPLLCR5 0x000017D8
+#define DDRSS_DDRPHY_DX8SLBDQSCTL 0x000017DC
+#define DDRSS_DDRPHY_DX8SLBTRNCTL 0x000017E0
+#define DDRSS_DDRPHY_DX8SLBDDLCTL 0x000017E4
+#define DDRSS_DDRPHY_DX8SLBDXCTL1 0x000017E8
+#define DDRSS_DDRPHY_DX8SLBDXCTL2 0x000017EC
+#define DDRSS_DDRPHY_DX8SLBIOCR 0x000017F0
+#define DDRSS_DDRPHY_DX4SLBIOCR 0x000017F4
+
+#define PIR_INIT_SHIFT 0
+#define PIR_INIT_MASK BIT(PIR_INIT_SHIFT)
+#define PIR_ZCAL_SHIFT 1
+#define PIR_ZCAL_MASK BIT(PIR_ZCAL_SHIFT)
+#define PIR_CA_SHIFT 2
+#define PIR_CA_MASK BIT(PIR_CA_SHIFT)
+#define PIR_PLLINIT_SHIFT 4
+#define PIR_PLLINIT_MASK BIT(PIR_PLLINIT_SHIFT)
+#define PIR_DCAL_SHIFT 5
+#define PIR_DCAL_MASK BIT(PIR_DCAL_SHIFT)
+#define PIR_PHYRST_SHIFT 6
+#define PIR_PHYRST_MASK BIT(PIR_PHYRST_SHIFT)
+#define PIR_DRAMRST_SHIFT 7
+#define PIR_DRAMRST_MASK BIT(PIR_DRAMRST_SHIFT)
+#define PIR_DRAMINIT_SHIFT 8
+#define PIR_DRAMINIT_MASK BIT(PIR_DRAMINIT_SHIFT)
+#define PIR_WL_SHIFT 9
+#define PIR_WL_MASK BIT(PIR_WL_SHIFT)
+#define PIR_QSGATE_SHIFT 10
+#define PIR_QSGATE_MASK BIT(PIR_QSGATE_SHIFT)
+#define PIR_WLADJ_SHIFT 11
+#define PIR_WLADJ_MASK BIT(PIR_WLADJ_SHIFT)
+#define PIR_RDDSKW_SHIFT 12
+#define PIR_RDDSKW_MASK BIT(PIR_RDDSKW_SHIFT)
+#define PIR_WRDSKW_SHIFT 13
+#define PIR_WRDSKW_MASK BIT(PIR_WRDSKW_SHIFT)
+#define PIR_RDEYE_SHIFT 14
+#define PIR_RDEYE_MASK BIT(PIR_RDEYE_SHIFT)
+#define PIR_WREYE_SHIFT 15
+#define PIR_WREYE_MASK BIT(PIR_WREYE_SHIFT)
+#define PIR_SRD_SHIFT 16
+#define PIR_SRD_MASK BIT(PIR_SRD_SHIFT)
+#define PIR_VREF_SHIFT 17
+#define PIR_VREF_MASK BIT(PIR_VREF_SHIFT)
+#define PIR_CTLDINIT_SHIFT 18
+#define PIR_CTLDINIT_MASK BIT(PIR_CTLDINIT_SHIFT)
+#define PIR_RDIMMINIT_SHIFT 19
+#define PIR_RDIMMINIT_MASK BIT(PIR_RDIMMINIT_SHIFT)
+#define PIR_DQS2DQ_SHIFT 20
+#define PIR_DQS2DQ_MASK BIT(PIR_DQS2DQ_SHIFT)
+#define PIR_DCALPSE_SHIFT 29
+#define PIR_DCALPSE_MASK BIT(PIR_DCALPSE_SHIFT)
+#define PIR_ZCALBYP_SHIFT 30
+#define PIR_ZCALBYP_MASK BIT(PIR_ZCALBYP_SHIFT)
+
+#define PIR_PHY_INIT (PIR_ZCAL_MASK | PIR_PLLINIT_MASK | \
+ PIR_DCAL_MASK | PIR_PHYRST_MASK)
+#define PIR_DRAM_INIT (PIR_DRAMRST_MASK | PIR_DRAMINIT_MASK)
+#define PIR_DATA_TR_INIT (PIR_WL_MASK | PIR_QSGATE_MASK | \
+ PIR_WLADJ_MASK | PIR_RDDSKW_MASK | \
+ PIR_WRDSKW_MASK | PIR_RDEYE_MASK \
+ PIR_WREYE_MASK)
+
+#define PGSR0_IDONE_SHIFT 0
+#define PGSR0_IDONE_MASK BIT(PGSR0_IDONE_SHIFT)
+#define PGSR0_PLDONE_SHIFT 1
+#define PGSR0_PLDONE_MASK BIT(PGSR0_PLDONE_SHIFT)
+#define PGSR0_DCDONE_SHIFT 2
+#define PGSR0_DCDONE_MASK BIT(PGSR0_DCDONE_SHIFT)
+#define PGSR0_ZCDONE_SHIFT 3
+#define PGSR0_ZCDONE_MASK BIT(PGSR0_ZCDONE_SHIFT)
+#define PGSR0_DIDONE_SHIFT 4
+#define PGSR0_DIDONE_MASK BIT(PGSR0_DIDONE_SHIFT)
+#define PGSR0_WLDONE_SHIFT 5
+#define PGSR0_WLDONE_MASK BIT(PGSR0_WLDONE_SHIFT)
+#define PGSR0_QSGDONE_SHIFT 6
+#define PGSR0_QSGDONE_MASK BIT(PGSR0_QSGDONE_SHIFT)
+#define PGSR0_WLADONE_SHIFT 7
+#define PGSR0_WLADONE_MASK BIT(PGSR0_WLADONE_SHIFT)
+#define PGSR0_RDDONE_SHIFT 8
+#define PGSR0_RDDONE_MASK BIT(PGSR0_RDDONE_SHIFT)
+#define PGSR0_WDDONE_SHIFT 9
+#define PGSR0_WDDONE_MASK BIT(PGSR0_WDDONE_SHIFT)
+#define PGSR0_REDONE_SHIFT 10
+#define PGSR0_REDONE_MASK BIT(PGSR0_REDONE_SHIFT)
+#define PGSR0_WEDONE_SHIFT 11
+#define PGSR0_WEDONE_MASK BIT(PGSR0_WEDONE_SHIFT)
+#define PGSR0_CADONE_SHIFT 12
+#define PGSR0_CADONE_MASK BIT(PGSR0_CADONE_SHIFT)
+#define PGSR0_SRDDONE_SHIFT 13
+#define PGSR0_SRDDONE_MASK BIT(PGSR0_SRDDONE_SHIFT)
+#define PGSR0_VDONE_SHIFT 14
+#define PGSR0_VDONE_MASK BIT(PGSR0_VDONE_SHIFT)
+#define PGSR0_DQS2DQDONE_SHIFT 15
+#define PGSR0_DQS2DQDONE_MASK BIT(PGSR0_DQS2DQDONE_SHIFT)
+#define PGSR0_DQS2DQERR_SHIFT 18
+#define PGSR0_DQS2DQERR_MASK BIT(PGSR0_DQS2DQERR_SHIFT)
+#define PGSR0_VERR_SHIFT 19
+#define PGSR0_VERR_MASK BIT(PGSR0_VERR_SHIFT)
+#define PGSR0_ZCERR_SHIFT 20
+#define PGSR0_ZCERR_MASK BIT(PGSR0_ZCERR_SHIFT)
+#define PGSR0_WLERR_SHIFT 21
+#define PGSR0_WLERR_MASK BIT(PGSR0_WLERR_SHIFT)
+#define PGSR0_QSGERR_SHIFT 22
+#define PGSR0_QSGERR_MASK BIT(PGSR0_QSGERR_SHIFT)
+#define PGSR0_WLAERR_SHIFT 23
+#define PGSR0_WLAERR_MASK BIT(PGSR0_WLAERR_SHIFT)
+#define PGSR0_RDERR_SHIFT 24
+#define PGSR0_RDERR_MASK BIT(PGSR0_RDERR_SHIFT)
+#define PGSR0_WDERR_SHIFT 25
+#define PGSR0_WDERR_MASK BIT(PGSR0_WDERR_SHIFT)
+#define PGSR0_REERR_SHIFT 26
+#define PGSR0_REERR_MASK BIT(PGSR0_REERR_SHIFT)
+#define PGSR0_WEERR_SHIFT 27
+#define PGSR0_WEERR_MASK BIT(PGSR0_WEERR_SHIFT)
+#define PGSR0_CAERR_SHIFT 28
+#define PGSR0_CAERR_MASK BIT(PGSR0_CAERR_SHIFT)
+#define PGSR0_CAWRN_SHIFT 29
+#define PGSR0_CAWRN_MASK BIT(PGSR0_CAWRN_SHIFT)
+#define PGSR0_SRDERR_SHIFT 30
+#define PGSR0_SRDERR_MASK BIT(PGSR0_SRDERR_SHIFT)
+#define PGSR0_APLOCK_SHIFT 31
+#define PGSR0_APLOCK_MASK BIT(PGSR0_APLOCK_SHIFT)
+
+#define PGSR0_PHY_INIT_MASK (PGSR0_IDONE_MASK | PGSR0_PLDONE_MASK |\
+ PGSR0_DCDONE_MASK | PGSR0_ZCDONE_MASK |\
+ PGSR0_APLOCK_MASK)
+#define PGSR0_DRAM_INIT_MASK (PGSR0_PHY_INIT_MASK | \
+ PGSR0_DIDONE_MASK)
+#define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK)
+
+struct ddrss_ddrctl_reg_params {
+ u32 ddrctl_dfimisc;
+ u32 ddrctl_dfitmg0;
+ u32 ddrctl_dfitmg1;
+ u32 ddrctl_dfitmg2;
+ u32 ddrctl_init0;
+ u32 ddrctl_init1;
+ u32 ddrctl_init3;
+ u32 ddrctl_init4;
+ u32 ddrctl_init5;
+ u32 ddrctl_init6;
+ u32 ddrctl_init7;
+ u32 ddrctl_mstr;
+ u32 ddrctl_odtcfg;
+ u32 ddrctl_odtmap;
+ u32 ddrctl_rankctl;
+ u32 ddrctl_rfshctl0;
+ u32 ddrctl_rfshtmg;
+ u32 ddrctl_zqctl0;
+ u32 ddrctl_zqctl1;
+};
+
+struct ddrss_ddrctl_crc_params {
+ u32 ddrctl_crcparctl0;
+ u32 ddrctl_crcparctl1;
+ u32 ddrctl_crcparctl2;
+};
+
+struct ddrss_ddrctl_ecc_params {
+ u32 ddrctl_ecccfg0;
+};
+
+struct ddrss_ddrctl_map_params {
+ u32 ddrctl_addrmap0;
+ u32 ddrctl_addrmap1;
+ u32 ddrctl_addrmap2;
+ u32 ddrctl_addrmap3;
+ u32 ddrctl_addrmap4;
+ u32 ddrctl_addrmap5;
+ u32 ddrctl_addrmap6;
+ u32 ddrctl_addrmap7;
+ u32 ddrctl_addrmap8;
+ u32 ddrctl_addrmap9;
+ u32 ddrctl_addrmap10;
+ u32 ddrctl_addrmap11;
+ u32 ddrctl_dqmap0;
+ u32 ddrctl_dqmap1;
+ u32 ddrctl_dqmap4;
+ u32 ddrctl_dqmap5;
+};
+
+struct ddrss_ddrctl_pwr_params {
+ u32 ddrctl_pwrctl;
+};
+
+struct ddrss_ddrctl_timing_params {
+ u32 ddrctl_dramtmg0;
+ u32 ddrctl_dramtmg1;
+ u32 ddrctl_dramtmg2;
+ u32 ddrctl_dramtmg3;
+ u32 ddrctl_dramtmg4;
+ u32 ddrctl_dramtmg5;
+ u32 ddrctl_dramtmg6;
+ u32 ddrctl_dramtmg7;
+ u32 ddrctl_dramtmg8;
+ u32 ddrctl_dramtmg9;
+ u32 ddrctl_dramtmg11;
+ u32 ddrctl_dramtmg12;
+ u32 ddrctl_dramtmg13;
+ u32 ddrctl_dramtmg14;
+ u32 ddrctl_dramtmg15;
+ u32 ddrctl_dramtmg17;
+};
+
+struct ddrss_ddrphy_cfg_params {
+ u32 ddrphy_dcr;
+ u32 ddrphy_dsgcr;
+ u32 ddrphy_dx0gcr0;
+ u32 ddrphy_dx0gcr1;
+ u32 ddrphy_dx0gcr2;
+ u32 ddrphy_dx0gcr3;
+ u32 ddrphy_dx0gcr4;
+ u32 ddrphy_dx0gcr5;
+ u32 ddrphy_dx0gtr0;
+ u32 ddrphy_dx1gcr0;
+ u32 ddrphy_dx1gcr1;
+ u32 ddrphy_dx1gcr2;
+ u32 ddrphy_dx1gcr3;
+ u32 ddrphy_dx1gcr4;
+ u32 ddrphy_dx1gcr5;
+ u32 ddrphy_dx1gtr0;
+ u32 ddrphy_dx2gcr0;
+ u32 ddrphy_dx2gcr1;
+ u32 ddrphy_dx2gcr2;
+ u32 ddrphy_dx2gcr3;
+ u32 ddrphy_dx2gcr4;
+ u32 ddrphy_dx2gcr5;
+ u32 ddrphy_dx2gtr0;
+ u32 ddrphy_dx3gcr0;
+ u32 ddrphy_dx3gcr1;
+ u32 ddrphy_dx3gcr2;
+ u32 ddrphy_dx3gcr3;
+ u32 ddrphy_dx3gcr4;
+ u32 ddrphy_dx3gcr5;
+ u32 ddrphy_dx3gtr0;
+ u32 ddrphy_dx4gcr0;
+ u32 ddrphy_dx4gcr1;
+ u32 ddrphy_dx4gcr2;
+ u32 ddrphy_dx4gcr3;
+ u32 ddrphy_dx4gcr4;
+ u32 ddrphy_dx4gcr5;
+ u32 ddrphy_dx4gtr0;
+ u32 ddrphy_dx8sl0dxctl2;
+ u32 ddrphy_dx8sl0iocr;
+ u32 ddrphy_dx8sl0pllcr0;
+ u32 ddrphy_dx8sl1dxctl2;
+ u32 ddrphy_dx8sl1iocr;
+ u32 ddrphy_dx8sl1pllcr0;
+ u32 ddrphy_dx8sl2dxctl2;
+ u32 ddrphy_dx8sl2iocr;
+ u32 ddrphy_dx8sl2pllcr0;
+ u32 ddrphy_dxccr;
+ u32 ddrphy_odtcr;
+ u32 ddrphy_pgcr0;
+ u32 ddrphy_pgcr1;
+ u32 ddrphy_pgcr2;
+ u32 ddrphy_pgcr3;
+ u32 ddrphy_pgcr5;
+ u32 ddrphy_pgcr6;
+};
+
+struct ddrss_ddrphy_ctrl_params {
+ u32 ddrphy_dtcr0;
+ u32 ddrphy_dtcr1;
+ u32 ddrphy_mr0;
+ u32 ddrphy_mr1;
+ u32 ddrphy_mr2;
+ u32 ddrphy_mr3;
+ u32 ddrphy_mr4;
+ u32 ddrphy_mr5;
+ u32 ddrphy_mr6;
+ u32 ddrphy_mr11;
+ u32 ddrphy_mr12;
+ u32 ddrphy_mr13;
+ u32 ddrphy_mr14;
+ u32 ddrphy_mr22;
+ u32 ddrphy_pllcr0;
+ u32 ddrphy_vtcr0;
+};
+
+struct ddrss_ddrphy_ioctl_params {
+ u32 ddrphy_aciocr5;
+ u32 ddrphy_iovcr0;
+};
+
+struct ddrss_ddrphy_timing_params {
+ u32 ddrphy_dtpr0;
+ u32 ddrphy_dtpr1;
+ u32 ddrphy_dtpr2;
+ u32 ddrphy_dtpr3;
+ u32 ddrphy_dtpr4;
+ u32 ddrphy_dtpr5;
+ u32 ddrphy_dtpr6;
+ u32 ddrphy_ptr2;
+ u32 ddrphy_ptr3;
+ u32 ddrphy_ptr4;
+ u32 ddrphy_ptr5;
+ u32 ddrphy_ptr6;
+};
+
+struct ddrss_ddrphy_zq_params {
+ u32 ddrphy_zq0pr0;
+ u32 ddrphy_zq1pr0;
+ u32 ddrphy_zqcr;
+};
+
+struct ddrss_params {
+ struct ddrss_ddrctl_reg_params ctl_reg;
+ struct ddrss_ddrctl_crc_params ctl_crc;
+ struct ddrss_ddrctl_ecc_params ctl_ecc;
+ struct ddrss_ddrctl_map_params ctl_map;
+ struct ddrss_ddrctl_pwr_params ctl_pwr;
+ struct ddrss_ddrctl_timing_params ctl_timing;
+ struct ddrss_ddrphy_cfg_params phy_cfg;
+ struct ddrss_ddrphy_ctrl_params phy_ctrl;
+ struct ddrss_ddrphy_ioctl_params phy_ioctl;
+ struct ddrss_ddrphy_timing_params phy_timing;
+ struct ddrss_ddrphy_zq_params phy_zq;
+};
+
+#endif /* __K3_AM654_DDRSS_H */
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 597db4b9cbba9b644edeedcf01f9483cff23ff47..6625a65b584eccb39830b88607bf39c4fe6453ef 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -500,6 +500,12 @@ config BCM6345_SERIAL
help
Select this to enable UART on BCM6345 SoCs.
+config BCM6858_SERIAL
+ bool "Support for BCM6858 UART"
+ depends on DM_SERIAL && ARCH_BCM6858
+ help
+ Select this to enable UART on BCM6358 SoCs.
+
config FSL_LINFLEXUART
bool "Freescale Linflex UART support"
depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 03dc29ee2ec74f6842fdccab90dd25407af7f86c..a48458f95532a8e312bffb6fca988e75ccfcf276 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
+obj-$(CONFIG_BCM6858_SERIAL) += serial_bcm6858.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 1e6fc6c66839c844aaaf1c808633ba020b085fa2..f21c240e64aa2d7802841f719e8ddbb017d2f7be 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -148,10 +148,13 @@ int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
{
- serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
+ /* to keep serial format, read lcr before writing BKSE */
+ int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
+
+ serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
serial_out(baud_divisor & 0xff, &com_port->dll);
serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
- serial_out(UART_LCRVAL, &com_port->lcr);
+ serial_out(lcr_val, &com_port->lcr);
}
void NS16550_init(NS16550_t com_port, int baud_divisor)
@@ -181,6 +184,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(ns16550_getfcr(com_port), &com_port->fcr);
+ /* initialize serial config to 8N1 before writing baudrate */
+ serial_out(UART_LCRVAL, &com_port->lcr);
if (baud_divisor != -1)
NS16550_setbrg(com_port, baud_divisor);
#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \
@@ -348,6 +353,39 @@ static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
return 0;
}
+static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
+{
+ struct NS16550 *const com_port = dev_get_priv(dev);
+ int lcr_val = UART_LCR_WLS_8;
+ uint parity = SERIAL_GET_PARITY(serial_config);
+ uint bits = SERIAL_GET_BITS(serial_config);
+ uint stop = SERIAL_GET_STOP(serial_config);
+
+ /*
+ * only parity config is implemented, check if other serial settings
+ * are the default one.
+ */
+ if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP)
+ return -ENOTSUPP; /* not supported in driver*/
+
+ switch (parity) {
+ case SERIAL_PAR_NONE:
+ /* no bits to add */
+ break;
+ case SERIAL_PAR_ODD:
+ lcr_val |= UART_LCR_PEN;
+ break;
+ case SERIAL_PAR_EVEN:
+ lcr_val |= UART_LCR_PEN | UART_LCR_EPS;
+ break;
+ default:
+ return -ENOTSUPP; /* not supported in driver*/
+ }
+
+ serial_out(lcr_val, &com_port->lcr);
+ return 0;
+}
+
int ns16550_serial_probe(struct udevice *dev)
{
struct NS16550 *const com_port = dev_get_priv(dev);
@@ -454,6 +492,7 @@ const struct dm_serial_ops ns16550_serial_ops = {
.pending = ns16550_serial_pending,
.getc = ns16550_serial_getc,
.setbrg = ns16550_serial_setbrg,
+ .setconfig = ns16550_serial_setconfig
};
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/drivers/serial/serial_bcm6858.c b/drivers/serial/serial_bcm6858.c
new file mode 100644
index 0000000000000000000000000000000000000000..8aa37055f0bf8369e387efccabc0d235523693c1
--- /dev/null
+++ b/drivers/serial/serial_bcm6858.c
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Derived from linux/drivers/tty/serial/serial_bcm6345.c
+ * Copyright (C) 2017 Ãlvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <debug_uart.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/types.h>
+
+/* UART Control register */
+#define UART_CTL_REG 0x0
+#define UART_CTL_RXTIMEOUT_MASK 0x1f
+#define UART_CTL_RXTIMEOUT_5 0x5
+#define UART_CTL_RSTRXFIFO_SHIFT 6
+#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
+#define UART_CTL_RSTTXFIFO_SHIFT 7
+#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
+#define UART_CTL_STOPBITS_SHIFT 8
+#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
+#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
+#define UART_CTL_BITSPERSYM_SHIFT 12
+#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
+#define UART_CTL_BITSPERSYM_8 (0x3 << UART_CTL_BITSPERSYM_SHIFT)
+#define UART_CTL_XMITBRK_SHIFT 14
+#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
+#define UART_CTL_RSVD_SHIFT 15
+#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
+#define UART_CTL_RXPAREVEN_SHIFT 16
+#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
+#define UART_CTL_RXPAREN_SHIFT 17
+#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
+#define UART_CTL_TXPAREVEN_SHIFT 18
+#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
+#define UART_CTL_TXPAREN_SHIFT 19
+#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
+#define UART_CTL_LOOPBACK_SHIFT 20
+#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
+#define UART_CTL_RXEN_SHIFT 21
+#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
+#define UART_CTL_TXEN_SHIFT 22
+#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
+#define UART_CTL_BRGEN_SHIFT 23
+#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
+
+/* UART Baudword register */
+#define UART_BAUD_REG 0x4
+
+/* UART FIFO Config register */
+#define UART_FIFO_CFG_REG 0x8
+#define UART_FIFO_CFG_RX_SHIFT 8
+#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT)
+#define UART_FIFO_CFG_RX_4 (0x4 << UART_FIFO_CFG_RX_SHIFT)
+#define UART_FIFO_CFG_TX_SHIFT 12
+#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT)
+#define UART_FIFO_CFG_TX_4 (0x4 << UART_FIFO_CFG_TX_SHIFT)
+
+/* UART Interrupt register */
+#define UART_IR_REG 0x10
+#define UART_IR_STAT(x) (1 << (x))
+#define UART_IR_TXEMPTY 5
+#define UART_IR_RXOVER 7
+#define UART_IR_RXNOTEMPTY 11
+
+/* UART FIFO register */
+#define UART_FIFO_REG 0x14
+#define UART_FIFO_VALID_MASK 0xff
+#define UART_FIFO_FRAMEERR_SHIFT 8
+#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
+#define UART_FIFO_PARERR_SHIFT 9
+#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
+#define UART_FIFO_BRKDET_SHIFT 10
+#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
+#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
+ UART_FIFO_PARERR_MASK | \
+ UART_FIFO_BRKDET_MASK)
+
+struct bcm6858_serial_priv {
+ void __iomem *base;
+ ulong uartclk;
+};
+
+/* enable rx & tx operation on uart */
+static void bcm6858_serial_enable(void __iomem *base)
+{
+ setbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
+ UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
+}
+
+/* disable rx & tx operation on uart */
+static void bcm6858_serial_disable(void __iomem *base)
+{
+ clrbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
+ UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
+}
+
+/* clear all unread data in rx fifo and unsent data in tx fifo */
+static void bcm6858_serial_flush(void __iomem *base)
+{
+ /* empty rx and tx fifo */
+ setbits_le32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
+ UART_CTL_RSTTXFIFO_MASK);
+
+ /* read any pending char to make sure all irq status are cleared */
+ readl(base + UART_FIFO_REG);
+}
+
+static int bcm6858_serial_init(void __iomem *base, ulong clk, u32 baudrate)
+{
+ u32 val;
+
+ /* mask all irq and flush port */
+ bcm6858_serial_disable(base);
+ bcm6858_serial_flush(base);
+
+ /* set uart control config */
+ clrsetbits_le32(base + UART_CTL_REG,
+ /* clear rx timeout */
+ UART_CTL_RXTIMEOUT_MASK |
+ /* clear stop bits */
+ UART_CTL_STOPBITS_MASK |
+ /* clear bits per symbol */
+ UART_CTL_BITSPERSYM_MASK |
+ /* clear xmit break */
+ UART_CTL_XMITBRK_MASK |
+ /* clear reserved bit */
+ UART_CTL_RSVD_MASK |
+ /* disable parity */
+ UART_CTL_RXPAREN_MASK |
+ UART_CTL_TXPAREN_MASK |
+ /* disable loopback */
+ UART_CTL_LOOPBACK_MASK,
+ /* set timeout to 5 */
+ UART_CTL_RXTIMEOUT_5 |
+ /* set 8 bits/symbol */
+ UART_CTL_BITSPERSYM_8 |
+ /* set 1 stop bit */
+ UART_CTL_STOPBITS_1 |
+ /* set parity to even */
+ UART_CTL_RXPAREVEN_MASK |
+ UART_CTL_TXPAREVEN_MASK);
+
+ /* set uart fifo config */
+ clrsetbits_le32(base + UART_FIFO_CFG_REG,
+ /* clear fifo config */
+ UART_FIFO_CFG_RX_MASK |
+ UART_FIFO_CFG_TX_MASK,
+ /* set fifo config to 4 */
+ UART_FIFO_CFG_RX_4 |
+ UART_FIFO_CFG_TX_4);
+
+ /* set baud rate */
+ val = ((clk / baudrate) >> 4);
+ if (val & 0x1)
+ val = (val >> 1);
+ else
+ val = (val >> 1) - 1;
+ writel(val, base + UART_BAUD_REG);
+
+ /* clear interrupts */
+ writel(0, base + UART_IR_REG);
+
+ /* enable uart */
+ bcm6858_serial_enable(base);
+
+ return 0;
+}
+
+static int bcm6858_serial_pending(struct udevice *dev, bool input)
+{
+ struct bcm6858_serial_priv *priv = dev_get_priv(dev);
+ u32 val = readl(priv->base + UART_IR_REG);
+
+ if (input)
+ return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
+ else
+ return !(val & UART_IR_STAT(UART_IR_TXEMPTY));
+}
+
+static int bcm6858_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct bcm6858_serial_priv *priv = dev_get_priv(dev);
+
+ return bcm6858_serial_init(priv->base, priv->uartclk, baudrate);
+}
+
+static int bcm6858_serial_putc(struct udevice *dev, const char ch)
+{
+ struct bcm6858_serial_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = readl(priv->base + UART_IR_REG);
+ if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
+ return -EAGAIN;
+
+ writel(ch, priv->base + UART_FIFO_REG);
+
+ return 0;
+}
+
+static int bcm6858_serial_getc(struct udevice *dev)
+{
+ struct bcm6858_serial_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = readl(priv->base + UART_IR_REG);
+ if (val & UART_IR_STAT(UART_IR_RXOVER))
+ setbits_le32(priv->base + UART_CTL_REG,
+ UART_CTL_RSTRXFIFO_MASK);
+
+ if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
+ return -EAGAIN;
+
+ val = readl(priv->base + UART_FIFO_REG);
+ if (val & UART_FIFO_ANYERR_MASK)
+ return -EAGAIN;
+
+ return val & UART_FIFO_VALID_MASK;
+}
+
+static int bcm6858_serial_probe(struct udevice *dev)
+{
+ struct bcm6858_serial_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
+
+ /* get address */
+ priv->base = dev_remap_addr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ /* get clock rate */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+ priv->uartclk = clk_get_rate(&clk);
+ clk_free(&clk);
+
+ /* initialize serial */
+ return bcm6858_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
+}
+
+static const struct dm_serial_ops bcm6858_serial_ops = {
+ .putc = bcm6858_serial_putc,
+ .pending = bcm6858_serial_pending,
+ .getc = bcm6858_serial_getc,
+ .setbrg = bcm6858_serial_setbrg,
+};
+
+static const struct udevice_id bcm6858_serial_ids[] = {
+ { .compatible = "brcm,bcm6858-uart" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6858_serial) = {
+ .name = "bcm6858-uart",
+ .id = UCLASS_SERIAL,
+ .of_match = bcm6858_serial_ids,
+ .probe = bcm6858_serial_probe,
+ .priv_auto_alloc_size = sizeof(struct bcm6858_serial_priv),
+ .ops = &bcm6858_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_BCM6858
+static inline void _debug_uart_init(void)
+{
+ void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+ bcm6858_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+}
+
+static inline void wait_xfered(void __iomem *base)
+{
+ do {
+ u32 val = readl(base + UART_IR_REG);
+ if (val & UART_IR_STAT(UART_IR_TXEMPTY))
+ break;
+ } while (1);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+ wait_xfered(base);
+ writel(ch, base + UART_FIFO_REG);
+ wait_xfered(base);
+}
+
+DEBUG_UART_FUNCS
+#endif
diff --git a/drivers/w1-eeprom/Kconfig b/drivers/w1-eeprom/Kconfig
index 4b7f3c4e0b84f29e0f61a9158a28b2f422fbc38f..34aca4b9001ab339089b135f0e920a27a0408b0d 100644
--- a/drivers/w1-eeprom/Kconfig
+++ b/drivers/w1-eeprom/Kconfig
@@ -18,6 +18,19 @@ config W1_EEPROM_DS24XXX
help
Maxim DS24 EEPROMs 1-Wire EEPROM support
+config W1_EEPROM_DS2502
+ bool "Enable Maxim DS2502 Add-Only Memory support"
+ depends on W1
+ help
+ Maxim DS2502 1-Wire add-only memory support.
+ This device has 128 bytes of data memory, organized as 4 pages of
+ 32 bytes and 8 out of band status bytes that may be used to redirect
+ pages, allowing data to be modified up to 4 times (by external
+ programming).
+
+ The device may be seen as a 32 byte memory, using the page redirection
+ or as a 128 byte memory, ignoring the page redirection.
+
config W1_EEPROM_SANDBOX
bool "Enable sandbox onewire EEPROM driver"
depends on W1
diff --git a/drivers/w1-eeprom/Makefile b/drivers/w1-eeprom/Makefile
index 03cc4c8ac8db79b56db9e00d6f21ace715773432..83f4008bb55f98c4e8815bb4f7b60954c1edb1a7 100644
--- a/drivers/w1-eeprom/Makefile
+++ b/drivers/w1-eeprom/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_W1_EEPROM) += w1-eeprom-uclass.o
obj-$(CONFIG_W1_EEPROM_DS24XXX) += ds24xxx.o
+obj-$(CONFIG_W1_EEPROM_DS2502) += ds2502.o
obj-$(CONFIG_W1_EEPROM_SANDBOX) += eep_sandbox.o
diff --git a/drivers/w1-eeprom/ds2502.c b/drivers/w1-eeprom/ds2502.c
new file mode 100644
index 0000000000000000000000000000000000000000..76ca460ed7f44869b0a3bc6c5abfcd7dcf639054
--- /dev/null
+++ b/drivers/w1-eeprom/ds2502.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for DS-2502 One wire "Add only Memory".
+ *
+ * The chip has 4 pages of 32 bytes.
+ * In addition it has 8 out of band status bytes that are used, by software,
+ * as page redirection bytes by an algorithm described in the data sheet.
+ * This is useful since data cannot be erased once written but it can be
+ * "patched" up to four times by switching pages.
+ *
+ * So, when a read request is entirely in the first page automatically
+ * apply the page redirection bytes (which allows the device to be seen as
+ * a 32 byte PROM, writable 4 times).
+ *
+ * If the read request is outside of or larger than the first page then read
+ * the raw data (which allows the device to be seen as a 128 byte PROM,
+ * writable once).
+ *
+ * Copyright (c) 2018 Flowbird
+ * Martin Fuzzey <martin.fuzzey@flowbird.group>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/err.h>
+#include <w1-eeprom.h>
+#include <w1.h>
+
+#define DS2502_PAGE_SIZE 32
+#define DS2502_PAGE_COUNT 4
+#define DS2502_STATUS_SIZE 8
+
+#define DS2502_CMD_READ_STATUS 0xAA
+#define DS2502_CMD_READ_GEN_CRC 0xC3
+
+/* u-boot crc8() is CCITT CRC8, we need x^8 + x^5 + x^4 + 1 LSB first */
+static unsigned int ds2502_crc8(const u8 *buf, int len)
+{
+ static const u8 poly = 0x8C; /* (1 + x^4 + x^5) + x^8 */
+ u8 crc = 0;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ u8 data = buf[i];
+ int j;
+
+ for (j = 0; j < 8; j++) {
+ u8 mix = (crc ^ data) & 1;
+
+ crc >>= 1;
+ if (mix)
+ crc ^= poly;
+ data >>= 1;
+ }
+ }
+ return crc;
+}
+
+static int ds2502_read(struct udevice *dev, u8 cmd,
+ int bytes_in_page, int pos,
+ u8 *buf, int bytes_for_user)
+{
+ int retry;
+ int ret = 0;
+
+ for (retry = 0; retry < 3; retry++) {
+ u8 pagebuf[DS2502_PAGE_SIZE + 1]; /* 1 byte for CRC8 */
+ u8 crc;
+ int i;
+
+ ret = w1_reset_select(dev);
+ if (ret)
+ return ret;
+
+ /* send read to end of page and generate CRC command */
+ pagebuf[0] = cmd;
+ pagebuf[1] = pos & 0xff;
+ pagebuf[2] = pos >> 8;
+ crc = ds2502_crc8(pagebuf, 3);
+ for (i = 0; i < 3; i++)
+ w1_write_byte(dev, pagebuf[i]);
+
+ /* Check command CRC */
+ ret = w1_read_byte(dev);
+ if (ret < 0) {
+ dev_dbg(dev, "Error %d reading command CRC\n", ret);
+ continue;
+ }
+
+ if (ret != crc) {
+ dev_dbg(dev,
+ "bad CRC8 for cmd %02x got=%02X exp=%02X\n",
+ cmd, ret, crc);
+ ret = -EIO;
+ continue;
+ }
+
+ /* read data and check CRC */
+ ret = w1_read_buf(dev, pagebuf, bytes_in_page + 1);
+ if (ret < 0) {
+ dev_dbg(dev, "Error %d reading data\n", ret);
+ continue;
+ }
+
+ crc = ds2502_crc8(pagebuf, bytes_in_page);
+ if (crc == pagebuf[bytes_in_page]) {
+ memcpy(buf, pagebuf, bytes_for_user);
+ ret = 0;
+ break;
+ }
+ dev_dbg(dev, "Bad CRC8 got=%02X exp=%02X pos=%04X\n",
+ pagebuf[bytes_in_page], crc, pos);
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static inline int ds2502_read_status_bytes(struct udevice *dev, u8 *buf)
+{
+ return ds2502_read(dev, DS2502_CMD_READ_STATUS,
+ DS2502_STATUS_SIZE, 0,
+ buf, DS2502_STATUS_SIZE);
+}
+
+/*
+ * Status bytes (from index 1) contain 1's complement page indirection
+ * So for N writes:
+ * N=1: ff ff ff ff ff ff ff 00
+ * N=2: ff fe ff ff ff ff ff 00
+ * N=3: ff fe fd ff ff ff ff 00
+ * N=4: ff fe fd fc ff ff ff 00
+ */
+static int ds2502_indirect_page(struct udevice *dev, u8 *status, int page)
+{
+ int page_seen = 0;
+
+ do {
+ u8 sb = status[page + 1];
+
+ if (sb == 0xff)
+ break;
+
+ page = ~sb & 0xff;
+
+ if (page >= DS2502_PAGE_COUNT) {
+ dev_err(dev,
+ "Illegal page redirection status byte %02x\n",
+ sb);
+ return -EINVAL;
+ }
+
+ if (page_seen & (1 << page)) {
+ dev_err(dev, "Infinite loop in page redirection\n");
+ return -EINVAL;
+ }
+
+ page_seen |= (1 << page);
+ } while (1);
+
+ return page;
+}
+
+static int ds2502_read_buf(struct udevice *dev, unsigned int offset,
+ u8 *buf, unsigned int count)
+{
+ unsigned int min_page = offset / DS2502_PAGE_SIZE;
+ unsigned int max_page = (offset + count - 1) / DS2502_PAGE_SIZE;
+ int xfered = 0;
+ u8 status_bytes[DS2502_STATUS_SIZE];
+ int i;
+ int ret;
+
+ if (min_page >= DS2502_PAGE_COUNT || max_page >= DS2502_PAGE_COUNT)
+ return -EINVAL;
+
+ if (min_page == 0 && max_page == 0) {
+ ret = ds2502_read_status_bytes(dev, status_bytes);
+ if (ret)
+ return ret;
+ } else {
+ /* Dummy one to one page redirection */
+ memset(status_bytes, 0xff, sizeof(status_bytes));
+ }
+
+ for (i = min_page; i <= max_page; i++) {
+ int page;
+ int pos;
+ int bytes_in_page;
+ int bytes_for_user;
+
+ page = ds2502_indirect_page(dev, status_bytes, i);
+ if (page < 0)
+ return page;
+ dev_dbg(dev, "page logical %d => physical %d\n", i, page);
+
+ pos = page * DS2502_PAGE_SIZE;
+ if (i == min_page)
+ pos += offset % DS2502_PAGE_SIZE;
+
+ bytes_in_page = DS2502_PAGE_SIZE - (pos % DS2502_PAGE_SIZE);
+
+ if (i == max_page)
+ bytes_for_user = count - xfered;
+ else
+ bytes_for_user = bytes_in_page;
+
+ ret = ds2502_read(dev, DS2502_CMD_READ_GEN_CRC,
+ bytes_in_page, pos,
+ &buf[xfered], bytes_for_user);
+ if (ret < 0)
+ return ret;
+
+ xfered += bytes_for_user;
+ }
+
+ return 0;
+}
+
+static int ds2502_probe(struct udevice *dev)
+{
+ struct w1_device *w1;
+
+ w1 = dev_get_parent_platdata(dev);
+ w1->id = 0;
+ return 0;
+}
+
+static const struct w1_eeprom_ops ds2502_ops = {
+ .read_buf = ds2502_read_buf,
+};
+
+static const struct udevice_id ds2502_id[] = {
+ { .compatible = "maxim,ds2502", .data = W1_FAMILY_DS2502 },
+ { },
+};
+
+U_BOOT_DRIVER(ds2502) = {
+ .name = "ds2502",
+ .id = UCLASS_W1_EEPROM,
+ .of_match = ds2502_id,
+ .ops = &ds2502_ops,
+ .probe = ds2502_probe,
+};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 02f4e1e32fc7505bb1b67c017868825fa582bf35..a911dba73a4c439d5f9101ed30eba5ccde3fd6d3 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -118,4 +118,14 @@ config IMX_WATCHDOG
Select this to enable the IMX and LSCH2 of Layerscape watchdog
driver.
+config WDT_AT91
+ bool "AT91 watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Microchip watchdog timer, which can be found on
+ some AT91 devices.
+
+config AT91_HW_WDT_TIMEOUT
+ bool "AT91 watchdog timeout specified"
+ depends on WDT_AT91
endmenu
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 08406caa0f9c29c6bc26b3e499c8f60164f3e625..a5c27b0f4cf86633066a571686fb608cc2d3121c 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
+obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o
obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610))
obj-y += imx_watchdog.o
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index fca2849918f8fc24986bb24a8537ef179858730d..13f8772e4130ac1e273c920d211eefc4491f5eff 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -2,7 +2,7 @@
/*
* [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
*
- * Watchdog driver for Atmel AT91SAM9x processors.
+ * Watchdog driver for AT91SAM9x processors.
*
* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
@@ -14,38 +14,47 @@
* write to this register. Inform Linux to it too
*/
-#include <common.h>
-#include <watchdog.h>
-#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <asm/arch/at91_wdt.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/*
* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
* use this to convert a watchdog
- * value from/to milliseconds.
+ * value from seconds.
*/
-#define ms_to_ticks(t) (((t << 8) / 1000) - 1)
-#define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
+#define WDT_SEC2TICKS(s) (((s) << 8) - 1)
/* Hardware timeout in seconds */
-#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT)
-#define WDT_HW_TIMEOUT 2
-#else
-#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT
-#endif
+#define WDT_MAX_TIMEOUT 16
+#define WDT_MIN_TIMEOUT 0
+#define WDT_DEFAULT_TIMEOUT 2
+
+struct at91_wdt_priv {
+ void __iomem *regs;
+ u32 regval;
+ u32 timeout;
+};
/*
* Set the watchdog time interval in 1/256Hz (write-once)
* Counter is 12 bit.
*/
-static int at91_wdt_settimeout(unsigned int timeout)
+static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags)
{
- unsigned int reg;
- at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
+ struct at91_wdt_priv *priv = dev_get_priv(dev);
+ u32 timeout = WDT_SEC2TICKS(timeout_s);
+
+ if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT)
+ timeout = priv->timeout;
/* Check if disabled */
- if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) {
+ if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) {
printf("sorry, watchdog is disabled\n");
return -1;
}
@@ -57,24 +66,71 @@ static int at91_wdt_settimeout(unsigned int timeout)
* 4096 / 256 = 16 seconds.
*/
- reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
+ priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
| AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
| AT91_WDT_MR_WDD(0xfff) /* restart at any time */
| AT91_WDT_MR_WDV(timeout); /* timer value */
- writel(reg, &wd->mr);
+ writel(priv->regval, priv->regs + AT91_WDT_MR);
+
+ return 0;
+}
+
+static int at91_wdt_stop(struct udevice *dev)
+{
+ struct at91_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Disable Watchdog Timer */
+ priv->regval |= AT91_WDT_MR_WDDIS;
+ writel(priv->regval, priv->regs + AT91_WDT_MR);
return 0;
}
-void hw_watchdog_reset(void)
+static int at91_wdt_reset(struct udevice *dev)
{
- at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
- writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr);
+ struct at91_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR);
+
+ return 0;
}
-void hw_watchdog_init(void)
+static const struct wdt_ops at91_wdt_ops = {
+ .start = at91_wdt_start,
+ .stop = at91_wdt_stop,
+ .reset = at91_wdt_reset,
+};
+
+static const struct udevice_id at91_wdt_ids[] = {
+ { .compatible = "atmel,at91sam9260-wdt" },
+ {}
+};
+
+static int at91_wdt_probe(struct udevice *dev)
{
- /* 16 seconds timer, resets enabled */
- at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
+ struct at91_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_remap_addr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+#ifdef CONFIG_AT91_HW_WDT_TIMEOUT
+ priv->timeout = dev_read_u32_default(dev, "timeout-sec",
+ WDT_DEFAULT_TIMEOUT);
+ debug("%s: timeout %d", __func__, priv->timeout);
+#endif
+
+ debug("%s: Probing wdt%u\n", __func__, dev->seq);
+
+ return 0;
}
+
+U_BOOT_DRIVER(at91_wdt) = {
+ .name = "at91_wdt",
+ .id = UCLASS_WDT,
+ .of_match = at91_wdt_ids,
+ .priv_auto_alloc_size = sizeof(struct at91_wdt_priv),
+ .ops = &at91_wdt_ops,
+ .probe = at91_wdt_probe,
+};
diff --git a/fs/Makefile b/fs/Makefile
index bad0c2cc33e9f632da7f1ca22178404f0ef1c7af..f21cd23f033b52bc0e9fb3b7d13b17ced32d85a7 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -5,6 +5,7 @@
# Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_FS_LOADER) += fs.o
obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
else
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 373fee78a99931e55dfc10f8308c92f624e9c0cb..5838eb347798e430e809e870c8112b985b151a8f 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -355,15 +355,16 @@
"boot_script_dhcp=boot.scr.uimg\0" \
BOOTENV_BOOT_TARGETS \
\
+ "boot_syslinux_conf=extlinux/extlinux.conf\0" \
"boot_extlinux=" \
"sysboot ${devtype} ${devnum}:${distro_bootpart} any " \
- "${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \
+ "${scriptaddr} ${prefix}${boot_syslinux_conf}\0" \
\
"scan_dev_for_extlinux=" \
"if test -e ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${prefix}extlinux/extlinux.conf; then " \
- "echo Found ${prefix}extlinux/extlinux.conf; " \
+ "${prefix}${boot_syslinux_conf}; then " \
+ "echo Found ${prefix}${boot_syslinux_conf}; " \
"run boot_extlinux; " \
"echo SCRIPT FAILED: continuing...; " \
"fi\0" \
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 0463e42048dfa942d82cf0d64099f07172c81b51..4e7e5209d476e1ad04c07ba77ffaaf5e72276c0b 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -12,16 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
#include <configs/ti_omap3_common.h>
#undef CONFIG_DM_I2C_COMPAT
@@ -176,8 +166,6 @@
/* Physical Memory Map */
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
/* FLASH and environment organization */
@@ -203,10 +191,6 @@
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
-#undef CONFIG_SPL_BSS_START_ADDR
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 65015df1317e496b11ee65d2ac8fc7544247d955..484c5ef2fe1d252a70ab06aa0476ae75bf37ef94 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -21,6 +21,12 @@
/* SPL Loader Configuration */
#ifdef CONFIG_TARGET_AM654_A53_EVM
#define CONFIG_SPL_TEXT_BASE 0x80080000
+#else
+#define CONFIG_SPL_TEXT_BASE 0x41c00000
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h
new file mode 100644
index 0000000000000000000000000000000000000000..1c0945e140f3f79e43e270c731d052c1c4408015
--- /dev/null
+++ b/include/configs/broadcom_bcm968580xref.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+ 230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS 24
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/*
+ * 6858
+ */
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+/* U-Boot */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * 968580xref
+ */
+
+#define CONFIG_ENV_SIZE (8 * 1024)
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index 0b240e7ebc32a229598f8106b1ad5e8cc47dbb91..c2882e6daf6c65e0b1b17dfd4bce999658600014 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -57,10 +57,6 @@
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/* Enable the watchdog */
-#define CONFIG_AT91SAM9_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-
/*
* Command line configuration.
*/
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 114b87e1b399e66412831877544ec51c518ac97c..28af575bf20339e5c7ba70a6370919db1f3ce86e 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -112,13 +112,6 @@
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
"dhcp"
-/* Enable the watchdog */
-#define CONFIG_AT91SAM9_WATCHDOG
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_HW_WATCHDOG
-#endif
-#define CONFIG_AT91_HW_WDT_TIMEOUT 15
-
#if !defined(CONFIG_SPL_BUILD)
/* USB configuration */
#define CONFIG_USB_ATMEL
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 4fdb0dd962e777d9d1cc3f53d824fa06cf2f4799..f283ab7fcab75d0496a7df7a248cf0238adecec2 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -85,13 +85,6 @@
#define CONFIG_RMII
#define CONFIG_AT91_WANTS_COMMON_PHY
-#define CONFIG_AT91SAM9_WATCHDOG
-#define CONFIG_AT91_HW_WDT_TIMEOUT 15
-#if !defined(CONFIG_SPL_BUILD)
-/* Enable the watchdog */
-#define CONFIG_HW_WATCHDOG
-#endif
-
/* USB */
#if defined(CONFIG_BOARD_TAURUS)
#define CONFIG_USB_ATMEL
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 55b9b45eecc93fc06d2ca2a2be698457095d5990..0f892e51d1954dfb812adf3604b77865f2484239 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -165,7 +165,9 @@
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
#ifdef CONFIG_SPL_OS_BOOT
/* FAT */
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index 80de3f3fed2beb3a6af5429ba404c5179a7cf195..63a7d55b88808c428c71ff243f5850262af30121 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -6,6 +6,9 @@
#ifndef __PINCTRL_H
#define __PINCTRL_H
+#define PINNAME_SIZE 10
+#define PINMUX_SIZE 40
+
/**
* struct pinconf_param - pin config parameters
*
@@ -66,6 +69,7 @@ struct pinconf_param {
* pointing a config node. (necessary for pinctrl_full)
* @set_state_simple: do needed pinctrl operations for a peripherl @periph.
* (necessary for pinctrl_simple)
+ * @get_pin_muxing: display the muxing of a given pin.
*/
struct pinctrl_ops {
int (*get_pins_count)(struct udevice *dev);
@@ -129,6 +133,24 @@ struct pinctrl_ops {
* @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
*/
int (*get_gpio_mux)(struct udevice *dev, int banknum, int index);
+
+ /**
+ * get_pin_muxing() - show pin muxing
+ *
+ * This allows to display the muxing of a given pin. It's useful for
+ * debug purpose to know if a pin is configured as GPIO or as an
+ * alternate function and which one.
+ * Typically it is used by a PINCTRL driver with knowledge of the SoC
+ * pinctrl setup.
+ *
+ * @dev: Pinctrl device to use
+ * @selector: Pin selector
+ * @buf Pin's muxing description
+ * @size Pin's muxing description length
+ * return 0 if OK, -ve on error
+ */
+ int (*get_pin_muxing)(struct udevice *dev, unsigned int selector,
+ char *buf, int size);
};
#define pinctrl_get_ops(dev) ((struct pinctrl_ops *)(dev)->driver->ops)
@@ -348,4 +370,41 @@ int pinctrl_decode_pin_config(const void *blob, int node);
*/
int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index);
+/**
+ * pinctrl_get_pin_muxing() - Returns the muxing description
+ *
+ * This allows to display the muxing description of the given pin for
+ * debug purpose
+ *
+ * @dev: Pinctrl device to use
+ * @selector Pin index within pin-controller
+ * @buf Pin's muxing description
+ * @size Pin's muxing description length
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf,
+ int size);
+
+/**
+ * pinctrl_get_pins_count() - display pin-controller pins number
+ *
+ * This allows to know the number of pins owned by a given pin-controller
+ *
+ * @dev: Pinctrl device to use
+ * @return pins number if OK, -ve on error
+ */
+int pinctrl_get_pins_count(struct udevice *dev);
+
+/**
+ * pinctrl_get_pin_name() - Returns the pin's name
+ *
+ * This allows to display the pin's name for debug purpose
+ *
+ * @dev: Pinctrl device to use
+ * @selector Pin index within pin-controller
+ * @buf Pin's name
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf,
+ int size);
#endif /* __PINCTRL_H */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 4ef0d0f0c01285cb314473b9a883cd525deafc86..1bc62d523ee8a9e4a3c00416184b6239604d9b0c 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -307,6 +307,18 @@ int uclass_first_device_err(enum uclass_id id, struct udevice **devp);
*/
int uclass_next_device(struct udevice **devp);
+/**
+ * uclass_next_device_err() - Get the next device in a uclass
+ *
+ * The device returned is probed if necessary, and ready for use
+ *
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the uclass if no error occurred, or -ENODEV if
+ * there is no next device.
+ * @return 0 if found, -ENODEV if not found, other -ve on error
+ */
+int uclass_next_device_err(struct udevice **devp);
+
/**
* uclass_first_device_check() - Get the first device in a uclass
*
@@ -381,4 +393,20 @@ int uclass_resolve_seq(struct udevice *dev);
#define uclass_foreach_dev_safe(pos, next, uc) \
list_for_each_entry_safe(pos, next, &uc->dev_head, uclass_node)
+/**
+ * uclass_foreach_dev_probe() - Helper function to iteration through devices
+ * of given uclass
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end. Devices are probed if necessary,
+ * and ready for use.
+ *
+ * @id: Uclass ID
+ * @dev: struct udevice * to hold the current device. Set to NULL when there
+ * are no more devices.
+ */
+#define uclass_foreach_dev_probe(id, dev) \
+ for (int _ret = uclass_first_device_err(id, &dev); !_ret && dev; \
+ _ret = uclass_next_device_err(&dev))
+
#endif
diff --git a/include/serial.h b/include/serial.h
index 020cd392e888e2c0bdc2e28b025257e489db774a..ec25db6e601aa3e44d71847294291eb76685998f 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -195,9 +195,7 @@ struct dm_serial_ops {
* Set up a new config for this device.
*
* @dev: Device pointer
- * @parity: parity to use
- * @bits: bits number to use
- * @stop: stop bits number to use
+ * @serial_config: number of bits, parity and number of stopbits to use
* @return 0 if OK, -ve on error
*/
int (*setconfig)(struct udevice *dev, uint serial_config);
diff --git a/include/w1.h b/include/w1.h
index 399177a12e34b5c651f0373905d35d950c3763ff..b958b1c92c2f3c3e39d6cbe913136c68d74d70ac 100644
--- a/include/w1.h
+++ b/include/w1.h
@@ -12,6 +12,7 @@
#define W1_FAMILY_DS24B33 0x23
#define W1_FAMILY_DS2431 0x2d
+#define W1_FAMILY_DS2502 0x09
#define W1_FAMILY_EEP_SANDBOX 0xfe
struct w1_device {
diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c
index d3b9a60e994f998be93e27f8e6875d6f178790e1..7e9fa9272e80bdf6d2deda20c284344a646b1ded 100644
--- a/lib/libfdt/fdt_region.c
+++ b/lib/libfdt/fdt_region.c
@@ -96,6 +96,9 @@ int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
break;
case FDT_END_NODE:
+ /* Depth must never go below -1 */
+ if (depth < 0)
+ return -FDT_ERR_BADSTRUCTURE;
include = want;
want = stack[depth--];
while (end > path && *--end != '/')
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 0627024e71c4bacf6374a898793f37d5fb8eee40..abfb0ff89fa988f5f65a44b9ff6a313ae43df0c2 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -82,7 +82,6 @@ CONFIG_AT91SAM9G20EK_2MMC
CONFIG_AT91SAM9G45EKES
CONFIG_AT91SAM9G45_LCD_BASE
CONFIG_AT91SAM9M10G45EK
-CONFIG_AT91SAM9_WATCHDOG
CONFIG_AT91_CAN
CONFIG_AT91_EFLASH
CONFIG_AT91_GPIO_PULLUP
diff --git a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py
new file mode 100644
index 0000000000000000000000000000000000000000..25394f1fafa58debcedf9859bee9aaac4841cd00
--- /dev/null
+++ b/test/py/tests/test_pinmux.py
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0
+
+import pytest
+import u_boot_utils
+
+@pytest.mark.buildconfigspec('cmd_pinmux')
+def test_pinmux_usage_1(u_boot_console):
+ """Test that 'pinmux' command without parameters displays
+ pinmux usage."""
+ output = u_boot_console.run_command('pinmux')
+ assert 'Usage:' in output
+
+@pytest.mark.buildconfigspec('cmd_pinmux')
+def test_pinmux_usage_2(u_boot_console):
+ """Test that 'pinmux status' executed without previous "pinmux dev"
+ command displays pinmux usage."""
+ output = u_boot_console.run_command('pinmux status')
+ assert 'Usage:' in output
+
+@pytest.mark.buildconfigspec('cmd_pinmux')
+@pytest.mark.boardspec('sandbox')
+def test_pinmux_status_all(u_boot_console):
+ """Test that 'pinmux status -a' displays pin's muxing."""
+ output = u_boot_console.run_command('pinmux status -a')
+ assert ('SCL : I2C SCL' in output)
+ assert ('SDA : I2C SDA' in output)
+ assert ('TX : Uart TX' in output)
+ assert ('RX : Uart RX' in output)
+ assert ('W1 : 1-wire gpio' in output)
+
+@pytest.mark.buildconfigspec('cmd_pinmux')
+@pytest.mark.boardspec('sandbox')
+def test_pinmux_list(u_boot_console):
+ """Test that 'pinmux list' returns the pin-controller list."""
+ output = u_boot_console.run_command('pinmux list')
+ assert 'sandbox_pinctrl' in output
+
+@pytest.mark.buildconfigspec('cmd_pinmux')
+def test_pinmux_dev_bad(u_boot_console):
+ """Test that 'pinmux dev' returns an error when trying to select a
+ wrong pin controller."""
+ pincontroller = 'bad_pin_controller_name'
+ output = u_boot_console.run_command('pinmux dev ' + pincontroller)
+ expected_output = 'Can\'t get the pin-controller: ' + pincontroller + '!'
+ assert (expected_output in output)
+
+@pytest.mark.buildconfigspec('cmd_pinmux')
+@pytest.mark.boardspec('sandbox')
+def test_pinmux_dev(u_boot_console):
+ """Test that 'pinmux dev' select the wanted pin controller."""
+ pincontroller = 'pinctrl'
+ output = u_boot_console.run_command('pinmux dev ' + pincontroller)
+ expected_output = 'dev: ' + pincontroller
+ assert (expected_output in output)
+
+@pytest.mark.buildconfigspec('cmd_pinmux')
+@pytest.mark.boardspec('sandbox')
+def test_pinmux_status(u_boot_console):
+ """Test that 'pinmux status' displays selected pincontroller's pin
+ muxing descriptions."""
+ output = u_boot_console.run_command('pinmux status')
+ assert ('SCL : I2C SCL' in output)
+ assert ('SDA : I2C SDA' in output)
+ assert ('TX : Uart TX' in output)
+ assert ('RX : Uart RX' in output)
+ assert ('W1 : 1-wire gpio' in output)
diff --git a/tools/k3_x509template.txt b/tools/k3_x509template.txt
new file mode 100644
index 0000000000000000000000000000000000000000..bd3a9ab05608ee397f994dde3eff751156785fbc
--- /dev/null
+++ b/tools/k3_x509template.txt
@@ -0,0 +1,48 @@
+ [ req ]
+ distinguished_name = req_distinguished_name
+ x509_extensions = v3_ca
+ prompt = no
+ dirstring_type = nobmp
+
+ [ req_distinguished_name ]
+ C = US
+ ST = TX
+ L = Dallas
+ O = Texas Instruments Incorporated
+ OU = Processors
+ CN = TI Support
+ emailAddress = support@ti.com
+
+ [ v3_ca ]
+ basicConstraints = CA:true
+ 1.3.6.1.4.1.294.1.1 = ASN1:SEQUENCE:boot_seq
+ 1.3.6.1.4.1.294.1.2 = ASN1:SEQUENCE:image_integrity
+ 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv
+# 1.3.6.1.4.1.294.1.4 = ASN1:SEQUENCE:encryption
+ 1.3.6.1.4.1.294.1.8 = ASN1:SEQUENCE:debug
+
+ [ boot_seq ]
+ certType = INTEGER:TEST_CERT_TYPE
+ bootCore = INTEGER:TEST_BOOT_CORE
+ bootCoreOpts = INTEGER:TEST_BOOT_ARCH_WIDTH
+ destAddr = FORMAT:HEX,OCT:TEST_BOOT_ADDR
+ imageSize = INTEGER:TEST_IMAGE_LENGTH
+
+ [ image_integrity ]
+ shaType = OID:2.16.840.1.101.3.4.2.3
+ shaValue = FORMAT:HEX,OCT:TEST_IMAGE_SHA_VAL
+
+ [ swrv ]
+ swrv = INTEGER:0
+
+# [ encryption ]
+# initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV
+# randomString = FORMAT:HEX,OCT:TEST_IMAGE_ENC_RS
+# iterationCnt = INTEGER:TEST_IMAGE_KEY_DERIVE_INDEX
+# salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT
+
+ [ debug ]
+ debugType = INTEGER:4
+ coreDbgEn = INTEGER:0
+ coreDbgSecEn = INTEGER:0
+ debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000