diff --git a/MAKEALL b/MAKEALL
index c3df6575e2fd4cdd76c9eac0d2476ba9df173d79..d592374049960a802f2adac10f075f6ac6715110 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -361,6 +361,8 @@ LIST_ARM9=" \
omap5912osk \
omap730p2 \
openrd_base \
+ openrd_client \
+ openrd_ultimate \
rd6281a \
sbc2410x \
scb9328 \
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 18572b9d37eff80fc9a16da7606a55d8e429ad27..fccd2cdaa85485366eb76ead7c573bc48f6d8519 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -107,18 +107,18 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
}
struct mx3_cpu_type mx31_cpu_type[] = {
- { .srev = 0x00, .v = "1.0" },
- { .srev = 0x10, .v = "1.1" },
- { .srev = 0x11, .v = "1.1" },
- { .srev = 0x12, .v = "1.15" },
- { .srev = 0x13, .v = "1.15" },
- { .srev = 0x14, .v = "1.2" },
- { .srev = 0x15, .v = "1.2" },
- { .srev = 0x28, .v = "2.0" },
- { .srev = 0x29, .v = "2.0" },
+ { .srev = 0x00, .v = 0x10 },
+ { .srev = 0x10, .v = 0x11 },
+ { .srev = 0x11, .v = 0x11 },
+ { .srev = 0x12, .v = 0x1F },
+ { .srev = 0x13, .v = 0x1F },
+ { .srev = 0x14, .v = 0x12 },
+ { .srev = 0x15, .v = 0x12 },
+ { .srev = 0x28, .v = 0x20 },
+ { .srev = 0x29, .v = 0x20 },
};
-char *get_cpu_rev(void)
+u32 get_cpu_rev(void)
{
u32 i, srev;
@@ -129,7 +129,8 @@ char *get_cpu_rev(void)
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev)
return mx31_cpu_type[i].v;
- return "unknown";
+
+ return srev | 0x8000;
}
char *get_reset_cause(void)
@@ -161,8 +162,12 @@ char *get_reset_cause(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
- printf("CPU: Freescale i.MX31 rev %s at %d MHz.",
- get_cpu_rev(), mx31_get_mcu_main_clk() / 1000000);
+ u32 srev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.",
+ (srev & 0xF0) >> 4, (srev & 0x0F),
+ ((srev & 0x8000) ? " unknown" : ""),
+ mx31_get_mcu_main_clk() / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
index 80723eac542506d0aebb8d91d4ee87fd99990f26..22d10f1de75a6a833b2955c457149598354537bb 100644
--- a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
+++ b/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
@@ -27,11 +27,13 @@
#ifndef _ASM_ARCH_KW88F6281_H
#define _ASM_ARCH_KW88F6281_H
-/* SOC specific definations */
+/* SOC specific definitions */
#define KW88F6281_REGS_PHYS_BASE 0xf1000000
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
-/* TCLK Core Clock defination*/
-#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+/* TCLK Core Clock definition */
+#ifndef CONFIG_SYS_TCLK
+#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+#endif
#endif /* _ASM_ARCH_KW88F6281_H */
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index 8dc6e82bc6787a221b27396aaf90a3cab74dd7c9..1ff917ed242d1f9d6d6e82c652e6746b6c7d41f1 100644
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -31,5 +31,6 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config);
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);
+void mxc_hw_watchdog_enable(void);
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index c830a0374e86ba5133b5b0a511214827a0317a5e..306f966139b867bc49fdfa2c3c7e973e4a67485e 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -105,7 +105,7 @@ struct iim_regs {
struct mx3_cpu_type {
u8 srev;
- char *v;
+ u32 v;
};
#define IOMUX_PADNUM_MASK 0x1ff
diff --git a/board/Marvell/openrd_base/Makefile b/board/Marvell/openrd/Makefile
similarity index 98%
rename from board/Marvell/openrd_base/Makefile
rename to board/Marvell/openrd/Makefile
index d6d0ed33791fde296abfe678ceab478f46c030a0..19020e435f9b4f99665e7a3ca94ad3267e7868a6 100644
--- a/board/Marvell/openrd_base/Makefile
+++ b/board/Marvell/openrd/Makefile
@@ -31,7 +31,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS := openrd_base.o
+COBJS := openrd.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/Marvell/openrd_base/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg
similarity index 100%
rename from board/Marvell/openrd_base/kwbimage.cfg
rename to board/Marvell/openrd/kwbimage.cfg
diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd/openrd.c
similarity index 80%
rename from board/Marvell/openrd_base/openrd_base.c
rename to board/Marvell/openrd/openrd.c
index 10109c1322a496b241469bb248b68e2337deecff..87939decf3cc49878ed89f3968b97195c0cecb78 100644
--- a/board/Marvell/openrd_base/openrd_base.c
+++ b/board/Marvell/openrd/openrd.c
@@ -31,7 +31,7 @@
#include <miiphy.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
-#include "openrd_base.h"
+#include "openrd.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -110,7 +110,13 @@ int board_init(void)
/*
* arch number of board
*/
+#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
+#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
+ gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
+#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+ gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
+#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
@@ -118,12 +124,11 @@ int board_init(void)
}
#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
+/* Configure and enable MV88E1116/88E1121 PHY */
+void mv_phy_init(char *name)
{
u16 reg;
u16 devadr;
- char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
@@ -148,6 +153,24 @@ void reset_phy(void)
/* reset the phy */
miiphy_reset(name, devadr);
- printf("88E1116 Initialized on %s\n", name);
+ printf(PHY_NO" Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+ mv_phy_init("egiga0");
+
+#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+ /* Kirkwood ethernet driver is written with the assumption that in case
+ * of multiple PHYs, their addresses are consecutive. But unfortunately
+ * in case of OpenRD-Client, PHY addresses are not consecutive.*/
+ miiphy_write("egiga1", 0xEE, 0xEE, 24);
+#endif
+
+#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
+ defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+ /* configure and initialize both PHY's */
+ mv_phy_init("egiga1");
+#endif
}
#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd/openrd.h
similarity index 100%
rename from board/Marvell/openrd_base/openrd_base.h
rename to board/Marvell/openrd/openrd.h
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index b088c9c3e3d2cdf194282f5e0ee0580de7f995f3..73eaa48b0b28d682e2c879ec7c094fa2a9e69876 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -179,12 +179,12 @@ int board_init(void)
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(0) |
+ DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
- DAVINCI_ABCR_TA(0) |
+ DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr); /* CS3 */
#endif
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 826fb4a86d9430bab38a9ca3a5db38dda2ef252a..08addd29e1fb3caa41c6fcbc51061cf00673f64b 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -28,9 +28,17 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ mxc_hw_watchdog_reset();
+}
+#endif
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@@ -68,6 +76,14 @@ int board_init(void)
return 0;
}
+int board_late_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ mxc_hw_watchdog_enable();
+#endif
+ return 0;
+}
+
int checkboard(void)
{
printf("Board: MX31PDK\n");
diff --git a/boards.cfg b/boards.cfg
index f0d3440c61c33243d554460996d307703fb54db9..4f48d196ae2312510f8fad7bd07af98f51a546a2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -108,7 +108,9 @@ suen8 arm arm926ejs km_arm keymile
mgcoge2un arm arm926ejs km_arm keymile kirkwood
guruplug arm arm926ejs - Marvell kirkwood
mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
-openrd_base arm arm926ejs - Marvell kirkwood
+openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE
+openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT
+openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE
rd6281a arm arm926ejs - Marvell kirkwood
sheevaplug arm arm926ejs - Marvell kirkwood
dockstar arm arm926ejs - Seagate kirkwood
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 103786209cfa972b7b17f41285b3070bf04d696c..6efbb02c161931d970d415aaeb223a9e53dd8255 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -24,6 +24,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <mxc_gpio.h>
+#include <errno.h>
/* GPIO port description */
static unsigned long gpio_ports[] = {
@@ -47,7 +48,7 @@ int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction)
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
- return 1;
+ return -EINVAL;
gpio &= 0x1f;
@@ -95,7 +96,7 @@ int mxc_gpio_get(unsigned int gpio)
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
- return -1;
+ return -EINVAL;
gpio &= 0x1f;
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index a8937dde2d481853a19ca3e96534e3475797abb7..0a392579557717eab5fe8cf89c9cf923bc8b0d9b 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -113,6 +113,9 @@
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* ====> Include platform Common Definitions */
+#include <asm/arch/config.h>
+
/*
* DRAM Banks configuration, Custom config can be done in <board>.h
*/
@@ -124,10 +127,7 @@
#endif
#endif /* CONFIG_NR_DRAM_BANKS */
-/* ====> Include platform Common Definations */
-#include <asm/arch/config.h>
-
-/* ====> Include driver Common Definations */
+/* ====> Include driver Common Definitions */
/*
* Common NAND configuration
*/
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index d4c6d16102f19a1c18a4605b5799e9cd9ec949b4..f5d3ee79a9c7f353464a83cdf06dacc30ed868d6 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -61,6 +61,7 @@
#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
+#define CONFIG_HW_WATCHDOG
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
@@ -98,6 +99,8 @@
*/
#undef CONFIG_CMD_IMLS
+#define BOARD_LATE_INIT
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/openrd_base.h b/include/configs/openrd.h
similarity index 81%
rename from include/configs/openrd_base.h
rename to include/configs/openrd.h
index cfdd09cda0e7395d54144bb35e60824d340a470a..3256cb36e54ca5330b20ff009a1db49edf66b92d 100644
--- a/include/configs/openrd_base.h
+++ b/include/configs/openrd.h
@@ -27,13 +27,25 @@
* MA 02110-1301 USA
*/
-#ifndef _CONFIG_OPENRD_BASE_H
-#define _CONFIG_OPENRD_BASE_H
+#ifndef _CONFIG_OPENRD_H
+#define _CONFIG_OPENRD_H
/*
* Version number information
*/
-#define CONFIG_IDENT_STRING "\nOpenRD_base"
+#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
+# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
+#else
+# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+# define CONFIG_IDENT_STRING "\nOpenRD-Client"
+# else
+# ifdef CONFIG_BOARD_IS_OPENRD_BASE
+# define CONFIG_IDENT_STRING "\nOpenRD-Base"
+# else
+# error Unknown OpenRD board specified
+# endif
+# endif
+#endif
/*
* High Level Configuration Options (easy to change)
@@ -48,6 +60,7 @@
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_DHCP
@@ -105,8 +118,18 @@
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0x8
+# ifdef CONFIG_BOARD_IS_OPENRD_BASE
+# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+# else
+# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
+# endif
+# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
+# define CONFIG_PHY_BASE_ADR 0x0
+# define PHY_NO "88E1121"
+# else
+# define CONFIG_PHY_BASE_ADR 0x8
+# define PHY_NO "88E1116"
+# endif
#endif /* CONFIG_CMD_NET */
/*