diff --git a/CREDITS b/CREDITS
index 26d5f51b99c791d3090637fd48284e27d02d7a92..e84ef38ea87247b3137683ac735521d28ab3f01f 100644
--- a/CREDITS
+++ b/CREDITS
@@ -435,6 +435,7 @@ D: Support for EP82xxM
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
+D: Support for ColdFire MCF5275
N: Michal Simek
E: monstr@monstr.eu
diff --git a/MAINTAINERS b/MAINTAINERS
index 31c0311312765d9223bdc477eebe8ba775eb9f47..64a168a7460afcdd049aa037b771871edc7b8086 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -655,10 +655,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
TASREG MCF5249
-Zachary P. Landau <zachary.landau@labxtechnologies.com>
-
- r5200 mcf52x2
-
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M52277EVB mcf5227x
diff --git a/MAKEALL b/MAKEALL
index 6728d3f6e3b6fef9c3895f281daea8aa07d07373..c781fa506eb63c384b2bdcf6906f8f2dc3539092 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -665,13 +665,13 @@ LIST_coldfire=" \
M5253EVB \
M5271EVB \
M5272C3 \
+ M5275EVB \
M5282EVB \
M5329AFEE \
M5373EVB \
M54455EVB \
M5475AFE \
M5485AFE \
- r5200 \
TASREG \
"
diff --git a/Makefile b/Makefile
index cc60f1fa449d55acdf2353ddc9f9b37e991a1624..384d5a3df28896f237f01f509ea3fc0a1d6f42f4 100644
--- a/Makefile
+++ b/Makefile
@@ -1824,15 +1824,15 @@ M5271EVB_config : unconfig
M5272C3_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3
+M5275EVB_config : unconfig
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5275evb freescale
+
M5282EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb
TASREG_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd
-r5200_config : unconfig
- @$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
-
M5329AFEE_config \
M5329BFEE_config : unconfig
@case "$@" in \
diff --git a/board/r5200/Makefile b/board/freescale/m5275evb/Makefile
similarity index 75%
rename from board/r5200/Makefile
rename to board/freescale/m5275evb/Makefile
index 2ec71ee1d2711a631bc7bf7e6d84357b9d02db95..9a0fa80538736518531928c6a8c27d78b10a423c 100644
--- a/board/r5200/Makefile
+++ b/board/freescale/m5275evb/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -23,22 +23,18 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+OBJS = $(BOARD).o mii.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
#########################################################################
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-sinclude $(obj).depend
+sinclude .depend
#########################################################################
diff --git a/board/r5200/config.mk b/board/freescale/m5275evb/config.mk
similarity index 97%
rename from board/r5200/config.mk
rename to board/freescale/m5275evb/config.mk
index 8fc5319798df2de0a39d5ad322dcd520e1b6f8b2..ccb2cf735df3734a2b2c2429897e8168c76b7119 100644
--- a/board/r5200/config.mk
+++ b/board/freescale/m5275evb/config.mk
@@ -22,4 +22,4 @@
# MA 02111-1307 USA
#
-TEXT_BASE = 0x10000000
+TEXT_BASE = 0xffe00000
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
new file mode 100644
index 0000000000000000000000000000000000000000..a1b2902935f4f17f07c525cc44d7b2192085a8f1
--- /dev/null
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+#define PERIOD 13 /* system bus period in ns */
+#define SDRAM_TREFI 7800 /* in ns */
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale MCF5275 EVB\n");
+ return 0;
+};
+
+long int initdram(int board_type)
+{
+ volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+
+ gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+
+ /* Set up chip select */
+ sdp->sdbar0 = CFG_SDRAM_BASE;
+ sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+
+ /* Set up timing */
+ sdp->sdcfg1 = 0x83711630;
+ sdp->sdcfg2 = 0x46770000;
+
+ /* Enable clock */
+ sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+
+ /* Set precharge */
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+
+ /* Dummy write to start SDRAM */
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LEMR */
+ sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
+ | MCF_SDRAMC_SDMR_AD(0x0)
+ | MCF_SDRAMC_SDMR_CMD;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LMR */
+ sdp->sdmr = 0x058d0000;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+
+ /* Set precharge */
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop manual precharge, send 2 IREF */
+ sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Write mode register, clear reset DLL */
+ sdp->sdmr = 0x018d0000;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+ sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+
+ /* Turn on auto refresh, lock SDMR */
+ sdp->sdcr =
+ MCF_SDRAMC_SDCR_CKE
+ | MCF_SDRAMC_SDCR_REF
+ | MCF_SDRAMC_SDCR_MUX(1)
+ /* 1 added to round up */
+ | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
+ | MCF_SDRAMC_SDCR_DQS_OE(0x3);
+
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/r5200/mii.c b/board/freescale/m5275evb/mii.c
similarity index 92%
rename from board/r5200/mii.c
rename to board/freescale/m5275evb/mii.c
index 706c90f6435a49f71a4c84f221709cdcedd97a7e..bbc93f6d4832f076812a00b0568035e6d4960666 100644
--- a/board/r5200/mii.c
+++ b/board/freescale/m5275evb/mii.c
@@ -36,10 +36,26 @@ DECLARE_GLOBAL_DATA_PTR;
int fecpin_setclear(struct eth_device *dev, int setclear)
{
+ struct fec_info_s *info = (struct fec_info_s *) dev->priv;
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
if (setclear) {
/* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ if (info->iobase == CFG_FEC0_IOBASE) {
+ gpio->par_feci2c |= 0x0F00;
+ gpio->par_fec0hl |= 0xC0;
+ } else {
+ gpio->par_feci2c |= 0x00A0;
+ gpio->par_fec1hl |= 0xC0;
+ }
} else {
+ if (info->iobase == CFG_FEC0_IOBASE) {
+ gpio->par_feci2c &= ~0x0F00;
+ gpio->par_fec0hl &= ~0xC0;
+ } else {
+ gpio->par_feci2c &= ~0x00A0;
+ gpio->par_fec1hl &= ~0xC0;
+ }
}
return 0;
@@ -131,7 +147,7 @@ uint mii_send(uint mii_cmd)
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
@@ -200,7 +216,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/r5200/u-boot.lds b/board/freescale/m5275evb/u-boot.lds
similarity index 81%
rename from board/r5200/u-boot.lds
rename to board/freescale/m5275evb/u-boot.lds
index 29fe58941b4b2ccebbde0467e8cef7819628a389..43d65001b39b3131311da188f352fd2c112d0f1e 100644
--- a/board/r5200/u-boot.lds
+++ b/board/freescale/m5275evb/u-boot.lds
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -33,37 +33,36 @@ SECTIONS
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
+ lib_generic/string.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ common/environment.o(.text)
*(.text)
*(.fixup)
@@ -84,8 +83,7 @@ SECTIONS
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
-
- .reloc :
+ .reloc :
{
__got_start = .;
*(.got)
@@ -115,7 +113,6 @@ SECTIONS
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
-
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
@@ -129,7 +126,7 @@ SECTIONS
__init_end = .;
__bss_start = .;
- .bss (NOLOAD) :
+ .bss :
{
_sbss = .;
*(.sbss) *(.scommon)
diff --git a/board/freescale/m54455evb/flash.c b/board/freescale/m54455evb/flash.c
index de2cca863a9923c5f1492d59250fa5016ffce285..6b50e8d82909f0534affa9548a5a29a583872cf6 100644
--- a/board/freescale/m54455evb/flash.c
+++ b/board/freescale/m54455evb/flash.c
@@ -95,6 +95,11 @@ typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+#define STM_ID_M25P16 0x20152015
+#define FLASH_M25P16 0x0055
+#endif
+
#define SYNC __asm__("nop")
/*-----------------------------------------------------------------------
@@ -111,6 +116,12 @@ void inline spin_wheel(void);
void flash_sync_real_protect(flash_info_t * info);
uchar intel_sector_protected(flash_info_t * info, ushort sector);
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt);
+int serial_flash_read_status(int chipsel);
+static int ser_flash_cs = 0;
+#endif
+
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
ulong flash_init(void)
@@ -119,6 +130,10 @@ ulong flash_init(void)
ulong size = 0;
ulong fbase = 0;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ dspi_init();
+#endif
+
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
memset(&flash_info[i], 0, sizeof(flash_info_t));
@@ -129,6 +144,11 @@ ulong flash_init(void)
case 1:
fbase = (ulong) CFG_FLASH1_BASE;
break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case 2:
+ fbase = (ulong) CFG_FLASH2_BASE;
+ break;
+#endif
}
flash_get_size((FPWV *) fbase, &flash_info[i]);
@@ -152,7 +172,6 @@ int flash_get_offsets(ulong base, flash_info_t * info)
{
int i, j, k;
int sectors, bs, banks;
- ulong start;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
int sect[] = CFG_ATMEL_SECT;
@@ -196,6 +215,15 @@ int flash_get_offsets(ulong base, flash_info_t * info)
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
+ info->start[0] = CFG_FLASH2_BASE;
+ for (k = 0, i = 0; i < CFG_STM_SECT; i++, k++) {
+ info->start[k + 1] = info->start[k] + CFG_STM_SECTSZ;
+ info->protect[k] = 0;
+ }
+ }
+#endif
return ERR_OK;
}
@@ -211,6 +239,11 @@ void flash_print_info(flash_info_t * info)
case FLASH_MAN_ATM:
printf("ATMEL ");
break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ printf("ST ");
+ break;
+#endif
default:
printf("Unknown Vendor ");
break;
@@ -221,8 +254,13 @@ void flash_print_info(flash_info_t * info)
printf("AT49BV040A\n");
break;
case FLASH_28F128J3A:
- printf("Intel 28F128J3A\n");
+ printf("28F128J3A\n");
+ break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_M25P16:
+ printf("M25P16\n");
break;
+#endif
default:
printf("Unknown Chip Type\n");
return;
@@ -267,6 +305,45 @@ ulong flash_get_size(FPWV * addr, flash_info_t * info)
u16 value;
int i;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ if ((ulong) addr == CFG_FLASH2_BASE) {
+ int manufactId = 0;
+ int deviceId = 0;
+
+ ser_flash_cs = 1;
+
+ dspi_tx(ser_flash_cs, 0x80, SER_RDID);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+
+ dspi_rx();
+ manufactId = dspi_rx();
+ deviceId = dspi_rx() << 8;
+ deviceId |= dspi_rx();
+
+ dspi_tx(ser_flash_cs, 0x00, 0);
+ dspi_rx();
+
+ switch (manufactId) {
+ case (u8) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ }
+
+ switch (deviceId) {
+ case (u16) STM_ID_M25P16:
+ info->flash_id += FLASH_M25P16;
+ break;
+ }
+
+ info->sector_count = CFG_STM_SECT;
+ info->size = CFG_STM_SECT * CFG_STM_SECTSZ;
+
+ return (info->size);
+ }
+#endif
+
addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
@@ -383,6 +460,21 @@ int flash_cmd_rd(volatile u16 * addr, int index)
return (int)addr[index];
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int serial_flash_read_status(int chipsel)
+{
+ u16 status;
+
+ dspi_tx(chipsel, 0x80, SER_RDSR);
+ dspi_rx();
+
+ dspi_tx(chipsel, 0x00, 0);
+ status = dspi_rx();
+
+ return status;
+}
+#endif
+
/*
* This function gets the u-boot flash sector protection status
* (flash_info_t.protect[]) in sync with the sector protection
@@ -462,8 +554,11 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, last;
- int rcode = 0, intel = 0;
-
+ int rcode = 0, flashtype = 0;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ int count;
+ u16 status;
+#endif
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
@@ -474,19 +569,25 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
type = (info->flash_id & FLASH_VENDMASK);
- if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
- if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
- type = (info->flash_id & FLASH_VENDMASK);
- printf
- ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
+ switch (type) {
+ case FLASH_MAN_ATM:
+ flashtype = 1;
+ break;
+ case FLASH_MAN_INTEL:
+ flashtype = 2;
+ break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ flashtype = 3;
+ break;
+#endif
+ default:
+ type = (info->flash_id & FLASH_VENDMASK);
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
}
- if (type == FLASH_MAN_INTEL)
- intel = 1;
-
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
@@ -503,6 +604,51 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
start = get_timer(0);
last = start;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ /* Perform bulk erase */
+ if (flashtype == 3) {
+ if ((s_last - s_first) == (CFG_STM_SECT - 1)) {
+ if (prot == 0) {
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+
+ status = serial_flash_read_status(ser_flash_cs);
+ if (((status & 0x9C) != 0)
+ && ((status & 0x02) != 0x02)) {
+ printf("Can't erase flash\n");
+ return 1;
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, SER_BULK_ERASE);
+ dspi_rx();
+
+ count = 0;
+ start = get_timer(0);
+ do {
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+
+ if (count++ > 0x10000) {
+ spin_wheel();
+ count = 0;
+ }
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ printf("\b. done\n");
+ return 0;
+ } else if (prot == CFG_STM_SECT) {
+ return 1;
+ }
+ }
+ }
+#endif
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
@@ -515,65 +661,116 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
- if (intel) {
- *addr = (FPW) INTEL_READID;
- min = addr[INTEL_CFI_TERB] & 0xff;
- min = 1 << min; /* ms */
- min = (min / info->sector_count) * 1000;
-
- /* start erase block */
- *addr = (FPW) INTEL_CLEAR; /* clear status register */
- *addr = (FPW) INTEL_ERASE; /* erase setup */
- *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
-
- while ((*addr & (FPW) INTEL_FINISHED) !=
- (FPW) INTEL_FINISHED) {
-
- if (get_timer(start) >
- CFG_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
- *addr = (FPW) INTEL_RESET; /* reset to read mode */
-
- rcode = 1;
- break;
+ switch (flashtype) {
+ case 1:
+ {
+ FPWV *base; /* first address in bank */
+ FPWV *atmeladdr;
+
+ flag = disable_interrupts();
+
+ atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
+ base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
+
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ *atmeladdr = (u8) 0x00300030; /* erase sector */
+
+ if (flag)
+ enable_interrupts();
+
+ while ((*atmeladdr & (u8) 0x00800080) !=
+ (u8) 0x00800080) {
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
}
- }
-
- *addr = (FPW) INTEL_RESET; /* resest to read mode */
- } else {
- FPWV *base; /* first address in bank */
- FPWV *atmeladdr;
-
- flag = disable_interrupts();
- atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
- base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
-
- base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
- *atmeladdr = (u8) 0x00300030; /* erase sector */
+ *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+ break;
+ }
- if (flag)
- enable_interrupts();
+ case 2:
+ {
+ *addr = (FPW) INTEL_READID;
+ min = addr[INTEL_CFI_TERB] & 0xff;
+ min = 1 << min; /* ms */
+ min = (min / info->sector_count) * 1000;
+
+ /* start erase block */
+ *addr = (FPW) INTEL_CLEAR; /* clear status register */
+ *addr = (FPW) INTEL_ERASE; /* erase setup */
+ *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
+
+ while ((*addr & (FPW) INTEL_FINISHED) !=
+ (FPW) INTEL_FINISHED) {
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
+ *addr = (FPW) INTEL_RESET; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
+ }
- while ((*atmeladdr & (u8) 0x00800080) !=
- (u8) 0x00800080) {
- if (get_timer(start) >
- CFG_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+ *addr = (FPW) INTEL_RESET; /* resest to read mode */
+ break;
+ }
- rcode = 1;
- break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case 3:
+ {
+ u8 sec = ((ulong) addr >> 16) & 0xFF;
+
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+ if (((status & 0x9C) != 0)
+ && ((status & 0x02) != 0x02)) {
+ printf("Error Programming\n");
+ return 1;
}
- }
- *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
- } /* Atmel or Intel */
+ dspi_tx(ser_flash_cs, 0x80,
+ SER_SECT_ERASE);
+ dspi_tx(ser_flash_cs, 0x80, sec);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x00, 0);
+
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+
+ do {
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ break;
+ }
+#endif
+ } /* switch (flashtype) */
}
}
printf(" done\n");
@@ -583,6 +780,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
+ int count;
+
if (info->flash_id == FLASH_UNKNOWN)
return 4;
@@ -623,7 +822,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
u16 data;
- int count, i, l, rc, port_width;
+ int i, l, rc, port_width;
/* get lower word aligned address */
wp = addr;
@@ -724,6 +923,51 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
} /* case FLASH_MAN_INTEL */
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ {
+ ulong wp;
+ u8 *data = (u8 *) src;
+ int left; /* number of bytes left to program */
+
+ wp = addr;
+
+ /* page align, each page is 256 bytes */
+ if ((wp % 0x100) != 0) {
+ left = (0x100 - (wp & 0xFF));
+ write_ser_data(info, wp, data, left);
+ cnt -= left;
+ wp += left;
+ data += left;
+ }
+
+ /* page program - 256 bytes at a time */
+ if (cnt > 255) {
+ count = 0;
+ while (cnt >= 0x100) {
+ write_ser_data(info, wp, data, 0x100);
+ cnt -= 0x100;
+ wp += 0x100;
+ data += 0x100;
+
+ if (count++ > 0x400) {
+ spin_wheel();
+ count = 0;
+ }
+ }
+ }
+
+ /* remainint bytes */
+ if (cnt && (cnt < 256)) {
+ write_ser_data(info, wp, data, cnt);
+ wp += cnt;
+ data += cnt;
+ cnt -= cnt;
+ }
+
+ printf("\b.");
+ }
+#endif
} /* switch */
return ERR_OK;
@@ -844,6 +1088,75 @@ int write_data(flash_info_t * info, ulong dest, FPW data)
return (0);
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt)
+{
+ ulong start;
+ int status, i;
+ u8 flashdata;
+
+ /* Check if Flash is (sufficiently) erased */
+ dspi_tx(ser_flash_cs, 0x80, SER_READ);
+ dspi_tx(ser_flash_cs, 0x80, (dest >> 16) & 0xFF);
+ dspi_tx(ser_flash_cs, 0x80, (dest >> 8) & 0xFF);
+ dspi_tx(ser_flash_cs, 0x80, dest & 0xFF);
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ flashdata = dspi_rx();
+ dspi_tx(ser_flash_cs, 0x00, 0);
+ dspi_rx();
+
+ if ((flashdata & *data) != *data) {
+ printf("not erased at %08lx (%lx)\n", (ulong) dest,
+ (ulong) flashdata);
+ return (2);
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+
+ status = serial_flash_read_status(ser_flash_cs);
+ if (((status & 0x9C) != 0) && ((status & 0x02) != 0x02)) {
+ printf("Error Programming\n");
+ return 1;
+ }
+
+ start = get_timer(0);
+
+ dspi_tx(ser_flash_cs, 0x80, SER_PAGE_PROG);
+ dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF0000) >> 16));
+ dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF00) >> 8));
+ dspi_tx(ser_flash_cs, 0x80, (dest & 0xFF));
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+
+ for (i = 0; i < (cnt - 1); i++) {
+ dspi_tx(ser_flash_cs, 0x80, *data);
+ dspi_rx();
+ data++;
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, *data);
+ dspi_rx();
+
+ do {
+ status = serial_flash_read_status(ser_flash_cs);
+
+ if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ return (0);
+}
+#endif
+
/*-----------------------------------------------------------------------
* Write a word to Flash for ATMEL FLASH
* A word is 16 bits, whichever the bus width of the flash bank
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 0286084a8eeaa3fab82535ddd7df6d414e38aa1c..539da78de984782b161574ab1afea1ea2fb63265 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -43,6 +43,9 @@ long int initdram(int board_type)
volatile siu_t *siu = (siu_t *) (MMAP_SIU);
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
+#ifdef CFG_DRAMSZ1
+ u32 temp;
+#endif
siu->drv = CFG_SDRAM_DRVSTRENGTH;
diff --git a/board/r5200/r5200.c b/board/r5200/r5200.c
deleted file mode 100644
index 69f3a765b6176044a6f31be932971a7d34fefba5..0000000000000000000000000000000000000000
--- a/board/r5200/r5200.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-
-
-int checkboard (void) {
- puts ("Board: R5200 Ethernet Module\n");
- return 0;
-};
-
-long int initdram (int board_type) {
- int i;
-
- /*
- * Set CS2 pin to be SD_CS0
- */
- mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
- | MCF_GPIO_PAR_CS_PAR_CS2);
-
- mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM)
- | MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01));
-
- /*
- * Check to see if the SDRAM has already been initialized
- * by a run control tool
- */
- if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
- /*
- * Initialize DRAM Control Register: DCR
- */
- mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01)
- | MCF_SDRAMC_DCR_RC(0x30));
-
- /*
- * Initialize DACR0
- */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
- | MCF_SDRAMC_DACRn_CASL(0)
- | MCF_SDRAMC_DACRn_CBM(3)
- | MCF_SDRAMC_DACRn_PS(2));
-
- /*
- * Initialize DMR0
- */
- mbar_writeLong(MCF_SDRAMC_DMR0,
- MCF_SDRAMC_DMRn_BAM_8M
- | MCF_SDRAMC_DMRn_V);
-
- /*
- * Set IP bit in DACR
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_IP);
-
- /*
- * Wait at least 20ns to allow banks to precharge
- */
- for (i = 0; i < 5; i++)
- asm(" nop");
-
- /*
- * Write to this block to initiate precharge
- */
- *(u16 *)(CFG_SDRAM_BASE) = 0x9696;
-
- /*
- * Set RE bit in DACR
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_RE);
-
-
- /*
- * Wait for at least 8 auto refresh cycles to occur
- */
- for (i = 0; i < 2000; i++)
- asm(" nop");
-
- /*
- * Finish the configuration by issuing the MRS.
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_MRS);
-
-
- /*
- * Write to the SDRAM Mode Register
- */
- *(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696;
- }
-
- return CFG_SDRAM_SIZE * 1024 * 1024;
-};
-
-int testdram (void) {
- /* TODO: XXX XXX XXX */
- printf ("DRAM test not implemented!\n");
-
- return (0);
-}
diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index 0e2db1261fe7023acbc33cdbd306bd4adb0b902a..1b47c9775df99f5d46837eaa3cfa71886babd483 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -354,3 +354,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S
index 2bd603db66902c22e29d10abeae6083b75189b7d..ad04c0984a8fdacbd6ad331731732d646b66a6f5 100644
--- a/cpu/mcf523x/start.S
+++ b/cpu/mcf523x/start.S
@@ -338,3 +338,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk
index c3899c507ec9e12e4a5efed15193a45f1ec7d7ea..650e340aee8deea980598f84c2022e332ed4791d 100644
--- a/cpu/mcf52x2/config.mk
+++ b/cpu/mcf52x2/config.mk
@@ -30,6 +30,7 @@ is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
+is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
@@ -47,6 +48,9 @@ endif
ifneq (,$(findstring CONFIG_M5272,$(is5272)))
PLATFORM_CPPFLAGS += -mcpu=5272
endif
+ifneq (,$(findstring CONFIG_M5275,$(is5275)))
+PLATFORM_CPPFLAGS += -mcpu=5275
+endif
ifneq (,$(findstring CONFIG_M5282,$(is5282)))
PLATFORM_CPPFLAGS += -mcpu=5282
endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 71ea408aa5e2e359ee94c84a7ef8c539583bc7b5..d5d3d339c51a125391ef7692449b4f68cfd9671c 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -6,6 +6,9 @@
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -180,6 +183,69 @@ int watchdog_init(void)
#endif /* #ifdef CONFIG_M5272 */
+#ifdef CONFIG_M5275
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+ udelay(1000);
+
+ rcm->rcr = RCM_RCR_SOFTRST;
+
+ /* we don't return! */
+ return 0;
+};
+
+int checkcpu(void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
+ strmhz(buf, CFG_CLK));
+ return 0;
+};
+
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdt->wsr = 0x5555;
+ wdt->wsr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->wsr = 0x5555; /* reset watchdog counter */
+ wdt->wsr = 0xAAAA;
+ wdt->wcr = 0; /* disable watchdog timer */
+
+ puts("WATCHDOG:disabled\n");
+ return (0);
+}
+
+int watchdog_init(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->wcr = 0; /* disable watchdog */
+
+ /* set timeout and enable watchdog */
+ wdt->wmr =
+ ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ wdt->wsr = 0x5555; /* reset watchdog counter */
+ wdt->wsr = 0xAAAA;
+
+ puts("WATCHDOG:enabled\n");
+ return (0);
+}
+#endif /* #ifdef CONFIG_WATCHDOG */
+
+#endif /* #ifdef CONFIG_M5275 */
+
#ifdef CONFIG_M5282
int checkcpu(void)
{
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 458b85ef144f4bb220aa78c5bfcad4f0364fbfdd..207a37e7d57c55bbb3888873dacb0eef1b507aed 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -10,6 +10,9 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -245,6 +248,114 @@ void uart_port_conf(void)
}
#endif /* #if defined(CONFIG_M5272) */
+#if defined(CONFIG_M5275)
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ /* if we come from RAM we assume the CPU is
+ * already initialized.
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+ volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
+ volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+ volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+
+ /* Kill watchdog so we can initialize the PLL */
+ wdog_reg->wcr = 0;
+
+ /* Memory Controller: */
+ /* Flash */
+ csctrl_reg->ar0 = CFG_AR0_PRELIM;
+ csctrl_reg->cr0 = CFG_CR0_PRELIM;
+ csctrl_reg->mr0 = CFG_MR0_PRELIM;
+
+#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
+ csctrl_reg->ar1 = CFG_AR1_PRELIM;
+ csctrl_reg->cr1 = CFG_CR1_PRELIM;
+ csctrl_reg->mr1 = CFG_MR1_PRELIM;
+#endif
+
+#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
+ csctrl_reg->ar2 = CFG_AR2_PRELIM;
+ csctrl_reg->cr2 = CFG_CR2_PRELIM;
+ csctrl_reg->mr2 = CFG_MR2_PRELIM;
+#endif
+
+#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
+ csctrl_reg->ar3 = CFG_AR3_PRELIM;
+ csctrl_reg->cr3 = CFG_CR3_PRELIM;
+ csctrl_reg->mr3 = CFG_MR3_PRELIM;
+#endif
+
+#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
+ csctrl_reg->ar4 = CFG_AR4_PRELIM;
+ csctrl_reg->cr4 = CFG_CR4_PRELIM;
+ csctrl_reg->mr4 = CFG_MR4_PRELIM;
+#endif
+
+#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
+ csctrl_reg->ar5 = CFG_AR5_PRELIM;
+ csctrl_reg->cr5 = CFG_CR5_PRELIM;
+ csctrl_reg->mr5 = CFG_MR5_PRELIM;
+#endif
+
+#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
+ csctrl_reg->ar6 = CFG_AR6_PRELIM;
+ csctrl_reg->cr6 = CFG_CR6_PRELIM;
+ csctrl_reg->mr6 = CFG_MR6_PRELIM;
+#endif
+
+#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
+ csctrl_reg->ar7 = CFG_AR7_PRELIM;
+ csctrl_reg->cr7 = CFG_CR7_PRELIM;
+ csctrl_reg->mr7 = CFG_MR7_PRELIM;
+#endif
+
+#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+
+#ifdef CONFIG_FSL_I2C
+ gpio_reg->par_feci2c = 0x000F;
+#endif
+
+ /* enable instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->par_uart |= UART0_ENABLE_MASK;
+ break;
+ case 1:
+ gpio->par_uart |= UART1_ENABLE_MASK;
+ break;
+ case 2:
+ gpio->par_uart |= UART2_ENABLE_MASK;
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5275) */
+
#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index 9167cec69884cb711541e804e09ef36cb4155a0b..b8fb7bb0eecd710afb7fcae0bfa918495ce52876 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -59,7 +59,7 @@ void dtimer_intr_setup(void)
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
@@ -81,7 +81,7 @@ void dtimer_intr_setup(void)
intp->imrl0 &= ~CFG_TMRINTR_MASK;
}
#endif /* CONFIG_MCFTMR */
-#endif /* CONFIG_M5282 | CONFIG_M5271 */
+#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
int interrupt_init(void)
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index bc1e20023b17f224142a6de5c03c1bda0c6049c2..85a5c4de38f9e4d11906e92b9fab539ab1759c5e 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -64,8 +64,18 @@ int get_clocks (void)
#endif /* CONFIG_M5249 || CONFIG_M5253 */
+#if defined(CONFIG_M5275)
+ volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+
+ /* Setup PLL */
+ pll->syncr = 0x01080000;
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+ pll->syncr = 0x01000000;
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+#endif
+
gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 260a09abf76ffdcdd1c1a8ff4451993f9b9556bc..2bc0df39cadccbcc13f51d8a00a1de98b67afe56 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -56,9 +56,7 @@
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_R5200)
-.long 0x400
-#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
@@ -160,7 +158,7 @@ _copy_flash:
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
nop
@@ -168,7 +166,7 @@ _after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %RAMBAR1
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
#endif
@@ -185,16 +183,15 @@ _after_flashbar_copy:
movec %d0, %VBR
#endif
-#ifdef CONFIG_R5200
- move.l #(_flash_setup-CFG_FLASH_BASE), %a0
- move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
- move.l #(CFG_INIT_RAM_ADDR), %a2
-_copy_flash:
- move.l (%a0)+, (%a2)+
- cmp.l %a0, %a1
- bgt.s _copy_flash
- jmp CFG_INIT_RAM_ADDR
-_after_flash_copy:
+#ifdef CONFIG_M5275
+ /* Initialize IPSBAR */
+ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
+ move.l %d0, 0x40000000
+/* movec %d0, %MBAR */
+
+ /* Initialize RAMBAR: locate SRAM and validate it */
+ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ movec %d0, %RAMBAR1
#endif
#if 0
@@ -219,24 +216,6 @@ _after_flash_copy:
/*------------------------------------------------------------------------------*/
-#ifdef CONFIG_R5200
-_flash_setup:
- /* CSAR0 */
- move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
- move.w %d0, 0x40000080
-
- /* CSCR0 */
- move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
- move.w %d0, 0x4000008A
-
- /* CSMR0 */
- move.l #0x001f0001, %d0 /* 2 MB, valid */
- move.l %d0, 0x40000084
-
- jmp _after_flash_copy.L
-_flash_setup_end:
-#endif
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@@ -394,6 +373,25 @@ icache_enable:
rts
#endif
+#if defined(CONFIG_M5275)
+/*
+ * Instruction cache only
+ */
+ .globl icache_enable
+icache_enable:
+ move.l #0x01400000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0x0000c000, %d0 /* Setup SDRAM caching */
+ movec %d0, %ACR0 /* Enable cache */
+ move.l #0x00000000, %d0 /* No other caching */
+ movec %d0, %ACR1 /* Enable cache */
+ move.l #0x80400100, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ moveq #1, %d0
+ move.l %d0, icache_state
+ rts
+#endif
+
#ifdef CONFIG_M5282
.globl icache_enable
icache_enable:
@@ -478,3 +476,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index 61be2eac695b122d81782849e198bc8fc8cd1d37..a524f70783088a35173cb564803f5b280b3a961c 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -333,3 +333,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile
index 26ec29895ee1cf771d942d21b030149b9d2fcaa3..a549fdd2a3fc263d1720dc764e1f4e4803acea8c 100644
--- a/cpu/mcf5445x/Makefile
+++ b/cpu/mcf5445x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
-COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c
new file mode 100644
index 0000000000000000000000000000000000000000..44d8505bcd530d0c91376500fd04f90f847131b7
--- /dev/null
+++ b/cpu/mcf5445x/dspi.c
@@ -0,0 +1,73 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+
+#if defined(CONFIG_CF_DSPI)
+#include <asm/immap.h>
+void dspi_init(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
+ GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK;
+
+ dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
+ DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
+ DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
+ DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
+
+ dspi->dctar0 = DSPI_DCTAR_TRSZ(7) | DSPI_DCTAR_CPOL | DSPI_DCTAR_CPHA |
+ DSPI_DCTAR_PCSSCK_1CLK | DSPI_DCTAR_PASC(0) |
+ DSPI_DCTAR_PDT(0) | DSPI_DCTAR_CSSCK(0) |
+ DSPI_DCTAR_ASC(0) | DSPI_DCTAR_PBR(0) |
+ DSPI_DCTAR_DT(1) | DSPI_DCTAR_BR(1);
+}
+
+void dspi_tx(int chipsel, u8 attrib, u16 data)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x0000F000) >= 4) ;
+
+ dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
+}
+
+u16 dspi_rx(void)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x000000F0) == 0) ;
+
+ return (dspi->drfr & 0xFFFF);
+}
+
+#endif /* CONFIG_HARD_SPI */
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index d64c5af0db8771c9ded63545822fc75998267204..0c5194acdb03801e1d72c365ae21aef231111b4f 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -379,3 +379,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index 442665f2506e55708b1aa78facb348b8bc35a816..c12d7a0fcbb24605e422b30c460e3153a975aee3 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -359,3 +359,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
index 3c579d3cf7e1b7372f3423c898dc0659ac940ab9..8327e1b68acea3032e610f79b04de4a926af1a56 100644
--- a/include/asm-m68k/coldfire/dspi.h
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -64,10 +64,15 @@ typedef struct dspi {
#define DSPI_DMCR_CTXF (0x00000800)
#define DSPI_DMCR_DRXF (0x00001000)
#define DSPI_DMCR_DTXF (0x00002000)
+#define DSPI_DMCR_MDIS (0x00004000)
#define DSPI_DMCR_CSIS0 (0x00010000)
+#define DSPI_DMCR_CSIS1 (0x00020000)
#define DSPI_DMCR_CSIS2 (0x00040000)
#define DSPI_DMCR_CSIS3 (0x00080000)
+#define DSPI_DMCR_CSIS4 (0x00100000)
#define DSPI_DMCR_CSIS5 (0x00200000)
+#define DSPI_DMCR_CSIS6 (0x00400000)
+#define DSPI_DMCR_CSIS7 (0x00800000)
#define DSPI_DMCR_ROOE (0x01000000)
#define DSPI_DMCR_PCSSE (0x02000000)
#define DSPI_DMCR_MTFE (0x04000000)
@@ -92,6 +97,7 @@ typedef struct dspi {
#define DSPI_DCTAR_CPHA (0x02000000)
#define DSPI_DCTAR_CPOL (0x04000000)
#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
+#define DSPI_DCTAR_DBR (0x80000000)
#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
@@ -153,4 +159,8 @@ typedef struct dspi {
/* Bit definitions and macros for DRFDR group */
#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
+void dspi_init(void);
+void dspi_tx(int chipsel, u8 attrib, u16 data);
+u16 dspi_rx(void);
+
#endif /* __DSPI_H__ */
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 916bf966135bc172dc6e12855907d4e98cbdaa8b..f1586d5c75d1a1bf1e26dd11b5dd6c7350e0c2ff 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -180,6 +180,30 @@
#endif
#endif /* CONFIG_M5272 */
+#ifdef CONFIG_M5275
+#include <asm/immap_5275.h>
+#include <asm/m5275.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC0)
+#define CFG_FEC1_IOBASE (MMAP_FEC1)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (192)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0x1E)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5275 */
+
#ifdef CONFIG_M5282
#include <asm/immap_5282.h>
#include <asm/m5282.h>
diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h
new file mode 100644
index 0000000000000000000000000000000000000000..774866e34fac270bd878d6b2f03ab7f2e5ee61ea
--- /dev/null
+++ b/include/asm-m68k/immap_5275.h
@@ -0,0 +1,469 @@
+/*
+ * MCF5274/5 Internal Memory Map
+ *
+ * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
+ * Based on work Copyright (c) 2003 Josef Baumgartner
+ * <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5275__
+#define __IMMAP_5275__
+
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC0 (CFG_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400)
+#define MMAP_FEC1 (CFG_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_RCM (CFG_MBAR + 0x00110000)
+#define MMAP_CCM (CFG_MBAR + 0x00110004)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
+#define MMAP_USB (CFG_MBAR + 0x001C0000)
+#define MMAP_PWM0 (CFG_MBAR + 0x001D0000)
+
+/* System configuration registers
+*/
+typedef struct sys_ctrl {
+ u32 ipsbar;
+ u32 res1;
+ u32 rambar;
+ u32 res2;
+ u8 crsr;
+ u8 cwcr;
+ u8 lpicr;
+ u8 cwsr;
+ u8 res3[8];
+ u32 mpark;
+ u8 mpr;
+ u8 res4[3];
+ u8 pacr0;
+ u8 pacr1;
+ u8 pacr2;
+ u8 pacr3;
+ u8 pacr4;
+ u8 res5;
+ u8 pacr5;
+ u8 pacr6;
+ u8 pacr7;
+ u8 res6;
+ u8 pacr8;
+ u8 res7;
+ u8 gpacr;
+ u8 res8[3];
+} sysctrl_t;
+/* SDRAM controller registers, offset: 0x040
+ */
+typedef struct sdram_ctrl {
+ u32 sdmr;
+ u32 sdcr;
+ u32 sdcfg1;
+ u32 sdcfg2;
+ u32 sdbar0;
+ u32 sdbmr0;
+ u32 sdbar1;
+ u32 sdbmr1;
+} sdramctrl_t;
+
+/* Chip select module registers, offset: 0x080
+*/
+typedef struct cs_ctlr {
+ u16 ar0;
+ u16 res1;
+ u32 mr0;
+ u16 res2;
+ u16 cr0;
+ u16 ar1;
+ u16 res3;
+ u32 mr1;
+ u16 res4;
+ u16 cr1;
+ u16 ar2;
+ u16 res5;
+ u32 mr2;
+ u16 res6;
+ u16 cr2;
+ u16 ar3;
+ u16 res7;
+ u32 mr3;
+ u16 res8;
+ u16 cr3;
+ u16 ar4;
+ u16 res9;
+ u32 mr4;
+ u16 res10;
+ u16 cr4;
+ u16 ar5;
+ u16 res11;
+ u32 mr5;
+ u16 res12;
+ u16 cr5;
+ u16 ar6;
+ u16 res13;
+ u32 mr6;
+ u16 res14;
+ u16 cr6;
+ u16 ar7;
+ u16 res15;
+ u32 mr7;
+ u16 res16;
+ u16 cr7;
+} csctrl_t;
+
+/* DMA module registers, offset 0x100
+ */
+typedef struct dma_ctrl {
+ u32 sar;
+ u32 dar;
+ u32 dsrbcr;
+ u32 dcr;
+} dma_t;
+
+/* QSPI module registers, offset 0x340
+ */
+typedef struct qspi_ctrl {
+ u16 qmr;
+ u8 res1[2];
+ u16 qdlyr;
+ u8 res2[2];
+ u16 qwr;
+ u8 res3[2];
+ u16 qir;
+ u8 res4[2];
+ u16 qar;
+ u8 res5[2];
+ u16 qdr;
+ u8 res6[2];
+} qspi_t;
+
+/* Interrupt module registers, offset 0xc00
+*/
+typedef struct int_ctrl {
+ u32 iprh0;
+ u32 iprl0;
+ u32 imrh0;
+ u32 imrl0;
+ u32 frch0;
+ u32 frcl0;
+ u8 irlr;
+ u8 iacklpr;
+ u8 res1[0x26];
+ u8 icr0[64]; /* No ICR0, done this way for readability */
+ u8 res2[0x60];
+ u8 swiack0;
+ u8 res3[3];
+ u8 Lniack0_1;
+ u8 res4[3];
+ u8 Lniack0_2;
+ u8 res5[3];
+ u8 Lniack0_3;
+ u8 res6[3];
+ u8 Lniack0_4;
+ u8 res7[3];
+ u8 Lniack0_5;
+ u8 res8[3];
+ u8 Lniack0_6;
+ u8 res9[3];
+ u8 Lniack0_7;
+ u8 res10[3];
+} int0_t;
+
+/* GPIO port registers
+*/
+typedef struct gpio_ctrl {
+ /* Port Output Data Registers */
+ u8 podr_res1[4];
+ u8 podr_busctl;
+ u8 podr_addr;
+ u8 podr_res2[2];
+ u8 podr_cs;
+ u8 podr_res3;
+ u8 podr_fec0h;
+ u8 podr_fec0l;
+ u8 podr_feci2c;
+ u8 podr_qspi;
+ u8 podr_sdram;
+ u8 podr_timerh;
+ u8 podr_timerl;
+ u8 podr_uartl;
+ u8 podr_fec1h;
+ u8 podr_fec1l;
+ u8 podr_bs;
+ u8 podr_res4;
+ u8 podr_usbh;
+ u8 podr_usbl;
+ u8 podr_uarth;
+ u8 podr_res5[3];
+ /* Port Data Direction Registers */
+ u8 pddr_res1[4];
+ u8 pddr_busctl;
+ u8 pddr_addr;
+ u8 pddr_res2[2];
+ u8 pddr_cs;
+ u8 pddr_res3;
+ u8 pddr_fec0h;
+ u8 pddr_fec0l;
+ u8 pddr_feci2c;
+ u8 pddr_qspi;
+ u8 pddr_sdram;
+ u8 pddr_timerh;
+ u8 pddr_timerl;
+ u8 pddr_uartl;
+ u8 pddr_fec1h;
+ u8 pddr_fec1l;
+ u8 pddr_bs;
+ u8 pddr_res4;
+ u8 pddr_usbh;
+ u8 pddr_usbl;
+ u8 pddr_uarth;
+ u8 pddr_res5[3];
+ /* Port Pin Data/Set Registers */
+ u8 ppdsdr_res1[4];
+ u8 ppdsdr_busctl;
+ u8 ppdsdr_addr;
+ u8 ppdsdr_res2[2];
+ u8 ppdsdr_cs;
+ u8 ppdsdr_res3;
+ u8 ppdsdr_fec0h;
+ u8 ppdsdr_fec0l;
+ u8 ppdsdr_feci2c;
+ u8 ppdsdr_qspi;
+ u8 ppdsdr_sdram;
+ u8 ppdsdr_timerh;
+ u8 ppdsdr_timerl;
+ u8 ppdsdr_uartl;
+ u8 ppdsdr_fec1h;
+ u8 ppdsdr_fec1l;
+ u8 ppdsdr_bs;
+ u8 ppdsdr_res4;
+ u8 ppdsdr_usbh;
+ u8 ppdsdr_usbl;
+ u8 ppdsdr_uarth;
+ u8 ppdsdr_res5[3];
+ /* Port Clear Output Data Registers */
+ u8 pclrr_res1[4];
+ u8 pclrr_busctl;
+ u8 pclrr_addr;
+ u8 pclrr_res2[2];
+ u8 pclrr_cs;
+ u8 pclrr_res3;
+ u8 pclrr_fec0h;
+ u8 pclrr_fec0l;
+ u8 pclrr_feci2c;
+ u8 pclrr_qspi;
+ u8 pclrr_sdram;
+ u8 pclrr_timerh;
+ u8 pclrr_timerl;
+ u8 pclrr_uartl;
+ u8 pclrr_fec1h;
+ u8 pclrr_fec1l;
+ u8 pclrr_bs;
+ u8 pclrr_res4;
+ u8 pclrr_usbh;
+ u8 pclrr_usbl;
+ u8 pclrr_uarth;
+ u8 pclrr_res5[3];
+ /* Pin Assignment Registers */
+ u8 par_addr;
+ u8 par_cs;
+ u16 par_busctl;
+ u8 par_res1[2];
+ u16 par_usb;
+ u8 par_fec0hl;
+ u8 par_fec1hl;
+ u16 par_timer;
+ u16 par_uart;
+ u16 par_qspi;
+ u16 par_sdram;
+ u16 par_feci2c;
+ u8 par_bs;
+ u8 par_res2[3];
+} gpio_t;
+
+
+/* PWM module registers
+ */
+typedef struct pwm_ctrl {
+ u8 pwcr0;
+ u8 res1[3];
+ u8 pwcr1;
+ u8 res2[3];
+ u8 pwcr2;
+ u8 res3[7];
+ u8 pwwd0;
+ u8 res4[3];
+ u8 pwwd1;
+ u8 res5[3];
+ u8 pwwd2;
+ u8 res6[7];
+} pwm_t;
+
+/* Watchdog registers
+ */
+typedef struct wdog_ctrl {
+ u16 wcr;
+ u16 wmr;
+ u16 wcntr;
+ u16 wsr;
+ u8 res4[114];
+} wdog_t;
+
+/* USB module registers
+*/
+typedef struct usb {
+ u16 res1;
+ u16 fnr;
+ u16 res2;
+ u16 fnmr;
+ u16 res3;
+ u16 rfmr;
+ u16 res4;
+ u16 rfmmr;
+ u8 res5[3];
+ u8 far;
+ u32 asr;
+ u32 drr1;
+ u32 drr2;
+ u16 res6;
+ u16 specr;
+ u16 res7;
+ u16 ep0sr;
+ u32 iep0cfg;
+ u32 oep0cfg;
+ u32 ep1cfg;
+ u32 ep2cfg;
+ u32 ep3cfg;
+ u32 ep4cfg;
+ u32 ep5cfg;
+ u32 ep6cfg;
+ u32 ep7cfg;
+ u32 ep0ctl;
+ u16 res8;
+ u16 ep1ctl;
+ u16 res9;
+ u16 ep2ctl;
+ u16 res10;
+ u16 ep3ctl;
+ u16 res11;
+ u16 ep4ctl;
+ u16 res12;
+ u16 ep5ctl;
+ u16 res13;
+ u16 ep6ctl;
+ u16 res14;
+ u16 ep7ctl;
+ u32 ep0isr;
+ u16 res15;
+ u16 ep1isr;
+ u16 res16;
+ u16 ep2isr;
+ u16 res17;
+ u16 ep3isr;
+ u16 res18;
+ u16 ep4isr;
+ u16 res19;
+ u16 ep5isr;
+ u16 res20;
+ u16 ep6isr;
+ u16 res21;
+ u16 ep7isr;
+ u32 ep0imr;
+ u16 res22;
+ u16 ep1imr;
+ u16 res23;
+ u16 ep2imr;
+ u16 res24;
+ u16 ep3imr;
+ u16 res25;
+ u16 ep4imr;
+ u16 res26;
+ u16 ep5imr;
+ u16 res27;
+ u16 ep6imr;
+ u16 res28;
+ u16 ep7imr;
+ u32 ep0dr;
+ u32 ep1dr;
+ u32 ep2dr;
+ u32 ep3dr;
+ u32 ep4dr;
+ u32 ep5dr;
+ u32 ep6dr;
+ u32 ep7dr;
+ u16 res29;
+ u16 ep0dpr;
+ u16 res30;
+ u16 ep1dpr;
+ u16 res31;
+ u16 ep2dpr;
+ u16 res32;
+ u16 ep3dpr;
+ u16 res33;
+ u16 ep4dpr;
+ u16 res34;
+ u16 ep5dpr;
+ u16 res35;
+ u16 ep6dpr;
+ u16 res36;
+ u16 ep7dpr;
+ u8 res37[788];
+ u8 cfgram[1024];
+} usb_t;
+
+/* PLL module registers
+ */
+typedef struct pll_ctrl {
+ u32 syncr;
+ u32 synsr;
+} pll_t;
+
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+#endif /* __IMMAP_5275__ */
diff --git a/include/asm-m68k/m5275.h b/include/asm-m68k/m5275.h
new file mode 100644
index 0000000000000000000000000000000000000000..89c6c925942ce6a276b4139fcbb0a07ba3404064
--- /dev/null
+++ b/include/asm-m68k/m5275.h
@@ -0,0 +1,241 @@
+/*
+ * MCF5275 Internal Memory Map
+ *
+ * Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com)
+ * Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M5275_H__
+#define __M5275_H__
+
+/*
+ * Define the 5275 SIM register set addresses. These are similar,
+ * but not quite identical to the 5282 registers and offsets.
+ */
+#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCF_GPIO_PAR_UART 0x10007c
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x00f0
+#define UART2_ENABLE_MASK 0x3f00
+
+#define MCF_GPIO_PAR_FECI2C 0x100082
+#define PAR_SDA_ENABLE_MASK 0x0003
+#define PAR_SCL_ENABLE_MASK 0x000c
+
+#define MCFSIM_WRRR 0x140000
+#define MCFSIM_SDCR 0x40
+
+/*********************************************************************
+ * SDRAM Controller (SDRAMC)
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
+#define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044]))
+#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
+#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
+#define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
+#define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058]))
+#define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
+#define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C]))
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD (0x00010000)
+#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
+#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
+#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
+#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
+#define MCF_SDRAMC_SDCR_IREF (0x00000004)
+#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10)
+#define MCF_SDRAMC_SDCR_DQP_BP (0x00008000)
+#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
+#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
+#define MCF_SDRAMC_SDCR_REF (0x10000000)
+#define MCF_SDRAMC_SDCR_CKE (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDBARn */
+#define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18)
+#define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMRn */
+#define MCF_SDRAMC_SDMRn_V (0x00000001)
+#define MCF_SDRAMC_SDMRn_WP (0x00000080)
+#define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18)
+#define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000)
+#define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000)
+#define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000)
+#define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000)
+#define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000)
+#define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000)
+#define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000)
+#define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000)
+#define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000)
+
+/*********************************************************************
+ * Interrupt Controller (INTC)
+ ********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM (8)
+#define INT0_LO_DMA0 (9)
+#define INT0_LO_DMA1 (10)
+#define INT0_LO_DMA2 (11)
+#define INT0_LO_DMA3 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC0_TXF (23)
+#define INT0_LO_FEC0_TXB (24)
+#define INT0_LO_FEC0_UN (25)
+#define INT0_LO_FEC0_RL (26)
+#define INT0_LO_FEC0_RXF (27)
+#define INT0_LO_FEC0_RXB (28)
+#define INT0_LO_FEC0_MII (29)
+#define INT0_LO_FEC0_LC (30)
+#define INT0_LO_FEC0_HBERR (31)
+#define INT0_HI_FEC0_GRA (32)
+#define INT0_HI_FEC0_EBERR (33)
+#define INT0_HI_FEC0_BABT (34)
+#define INT0_HI_FEC0_BABR (35)
+#define INT0_HI_PIT0 (36)
+#define INT0_HI_PIT1 (37)
+#define INT0_HI_PIT2 (38)
+#define INT0_HI_PIT3 (39)
+#define INT0_HI_RNG (40)
+#define INT0_HI_SKHA (41)
+#define INT0_HI_MDHA (42)
+#define INT0_HI_USB (43)
+#define INT0_HI_USB_EP0 (44)
+#define INT0_HI_USB_EP1 (45)
+#define INT0_HI_USB_EP2 (46)
+#define INT0_HI_USB_EP3 (47)
+/* 48-63 Reserved */
+
+/* 0-22 Reserved */
+#define INT1_LO_FEC1_TXF (23)
+#define INT1_LO_FEC1_TXB (24)
+#define INT1_LO_FEC1_UN (25)
+#define INT1_LO_FEC1_RL (26)
+#define INT1_LO_FEC1_RXF (27)
+#define INT1_LO_FEC1_RXB (28)
+#define INT1_LO_FEC1_MII (29)
+#define INT1_LO_FEC1_LC (30)
+#define INT1_LO_FEC1_HBERR (31)
+#define INT1_HI_FEC1_GRA (32)
+#define INT1_HI_FEC1_EBERR (33)
+#define INT1_HI_FEC1_BABT (34)
+#define INT1_HI_FEC1_BABR (35)
+/* 36-63 Reserved */
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT (0x40)
+#define RCM_RCR_SOFTRST (0x80)
+
+#define FMPLL_SYNSR_LOCK (0x00000008)
+
+#endif /* __M5275_H__ */
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index a3d7bc46355febfd5b4afde10f68f7a44715a7e9..3d2891354f882071f5681812d52c833eee48ea43 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -86,6 +86,7 @@
"save\0" \
""
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_LCD
diff --git a/include/configs/r5200.h b/include/configs/M5275EVB.h
similarity index 55%
rename from include/configs/r5200.h
rename to include/configs/M5275EVB.h
index fc7658b9f2dc2c28e6283533fb57128febfd0fcc..599f8dcb4d0fb3610c64068c542516acab88a2dc 100644
--- a/include/configs/r5200.h
+++ b/include/configs/M5275EVB.h
@@ -1,9 +1,11 @@
/*
- * Configuation settings for the R5200 board
+ * Configuation settings for the Motorola MC5275EVB board.
*
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * Based on Motorola MC5272C3 board config
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ * By Arthur Shipkowski <art@videon-central.com>
+ * Copyright (C) 2005 Videon Central, Inc.
+ *
+ * Based off of M5272C3 board code by Josef Baumgartner
+ * <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,42 +30,38 @@
* board/config.h - configuration options, board specific
*/
-#ifndef _R5200_H
-#define _R5200_H
+#ifndef _M5275EVB_H
+#define _M5275EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5271 /* define processor type */
-#define CONFIG_R5200 /* define board type */
+#define CONFIG_M5275 /* define processor type */
+#define CONFIG_M5275EVB /* define board type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#define CONFIG_WATCHDOG
-#define CONFIG_WATCHDOG_TIMEOUT 0xFFFF /* clock modulus */
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_ENV_OFFSET 0x20000
-#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
#else
-#define CFG_ENV_ADDR 0xf0020000
+#define CFG_ENV_ADDR 0xffe04000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#endif
-
/*
* BOOTP options
*/
@@ -72,64 +70,80 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
+/* Available command configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
-# define CONFIG_NET_MULTI 1
-# define CONFIG_MII 1
-# define CFG_DISCOVER_PHY
-# define CFG_RX_ETH_BUFFER 8
-# define CFG_FAULT_ECHO_LINK_DOWN
-
-# define CFG_FEC0_PINMUX 0
-# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
+#define CFG_DISCOVER_PHY
+#define CFG_RX_ETH_BUFFER 8
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CFG_FEC0_PINMUX 0
+#define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+#define CFG_FEC1_PINMUX 0
+#define CFG_FEC1_MIIBASE CFG_FEC1_IOBASE
+#define MCFFEC_TOUT_LOOP 50000
+#define CONFIG_HAS_ETH1
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CFG_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CFG_FAULT_ECHO_LINK_DOWN
-# define CFG_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CFG_DISCOVER_PHY */
+#ifndef CFG_DISCOVER_PHY
+#define FECDUPLEX FULL
+#define FECSPEED _100BASET
+#else
+#ifndef CFG_FAULT_ECHO_LINK_DOWN
+#define CFG_FAULT_ECHO_LINK_DOWN
+#endif
+#endif
#endif
-/* Note: We only copy one sectors worth of application code from location
- * 10200000 for speed purposes. Increase the size if necessary */
-#define CONFIG_BOOTCOMMAND "cp.b 10200000 0 20000; go 400"
-#define CONFIG_BOOTDELAY 1
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
-#define CFG_PROMPT "u-boot> "
-#define CFG_LONGHELP /* undef to save memory */
+#ifdef CONFIG_MCFFEC
+#define CONFIG_ETHADDR 00:06:3b:01:41:55
+#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60
+#endif
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if (CONFIG_CMD_KGDB)
+# define CFG_CBSIZE 1024
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+# define CFG_CBSIZE 256
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE CFG_CBSIZE
-#define CFG_LOAD_ADDR 0x00002000
+#define CFG_LOAD_ADDR 0x800000
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTCOMMAND "bootm ffe40000"
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
-#define CFG_HZ 1000000
-#define CFG_CLK 100000000
+#define CFG_HZ 1000
+#define CFG_CLK 150000000
/*
* Low Level Configuration Settings
@@ -137,16 +151,14 @@
* You should know what you are doing if you make changes here.
*/
-#define CFG_MBAR 0x40000000 /* Register Base Addrs */
-
-#define CFG_ENET_BD_BASE 0x480000
+#define CFG_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 1000 /* bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -156,16 +168,16 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
-#define CFG_FLASH_BASE 0x10000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_FLASH_BASE 0xffe00000
-#ifdef CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CFG_MONITOR_BASE 0x20000
#else
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#endif
-#define CFG_MONITOR_LEN 0x20001
+#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
@@ -174,18 +186,18 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial mmap for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
-#define CFG_FLASH_SIZE 0x800000
+#define CFG_FLASH_SIZE 0x200000
/*-----------------------------------------------------------------------
* Cache Configuration
@@ -195,10 +207,17 @@
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
+#define CFG_AR0_PRELIM (CFG_FLASH_BASE >> 16)
+#define CFG_CR0_PRELIM 0x1980
+#define CFG_MR0_PRELIM 0x001F0001
+
+#define CFG_AR1_PRELIM 0x3000
+#define CFG_CR1_PRELIM 0x1900
+#define CFG_MR1_PRELIM 0x00070001
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CFG_FECI2C 0xF0
+#define CFG_FECI2C 0x0FA0
-#endif /* _R5200_H */
+#endif /* _M5275EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 5f5576179eb33a061c69ff5be6eef6e6ce7cc18f..f33ccb0c80481a926713b966eb6b50a2342e8db1 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -171,6 +171,10 @@
#define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
@@ -309,7 +313,7 @@
#else
-# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+# define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
# define CFG_ATMEL_REGION 4
# define CFG_ATMEL_TOTALSECT 11
@@ -326,6 +330,28 @@
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
+#ifdef CONFIG_SERIAL_FLASH
+# define CFG_FLASH2_BASE 0x01000000
+# define CFG_STM_SECT 32
+# define CFG_STM_SECTSZ 0x10000
+
+# undef CFG_FLASH_ERASE_TOUT
+# define CFG_FLASH_ERASE_TOUT 20000
+
+# define SER_WREN 0x06
+# define SER_WRDI 0x04
+# define SER_RDID 0x9F
+# define SER_RDSR 0x05
+# define SER_WRSR 0x01
+# define SER_READ 0x03
+# define SER_F_READ 0x0B
+# define SER_PAGE_PROG 0x02
+# define SER_SECT_ERASE 0xD8
+# define SER_BULK_ERASE 0xC7
+# define SER_DEEP_PWRDN 0xB9
+# define SER_RES 0xAB
+#endif
+
#endif
/*