From 33d2e46591ef9e7805cfea8ed880d20b7bbcee7e Mon Sep 17 00:00:00 2001 From: Alison Wang <b18965@freescale.com> Date: Fri, 26 Dec 2014 13:14:01 +0800 Subject: [PATCH] ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> --- arch/arm/cpu/armv7/ls102xa/fdt.c | 13 +++++++++++++ arch/arm/include/asm/arch-ls102xa/config.h | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 0fda694bdd3..e0288b8c3fa 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -150,4 +150,17 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", "clock-frequency", busclk / 2, 1); + +#ifdef CONFIG_QSPI_BOOT + off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, + CONFIG_SYS_IFC_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +#else + off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, + QSPI0_BASE_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); + off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, + DSPI1_BASE_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +#endif } diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a06ef9dcbff..791551841c7 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -102,4 +102,8 @@ #error SoC not defined #endif +#define FSL_IFC_COMPAT "fsl,ifc" +#define FSL_QSPI_COMPAT "fsl,ls1-qspi" +#define FSL_DSPI_COMPAT "fsl,vf610-dspi" + #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ -- GitLab