diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 55ee36d0bc791bb1d228d928492a39a7cac3e412..bea8e10af7e19545c276d1371f8cdf809dc32b99 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,6 +34,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
@@ -286,6 +287,57 @@ void mpc85xx_reginfo(void)
print_lbc_regs();
}
+/* Common ddr init for non-corenet fsl 85xx platforms */
+#ifndef CONFIG_FSL_CORENET
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned int x = 10;
+ unsigned int i;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ out_be32(&gur->ddrdllcr, 0x81000000);
+ asm("sync;isync;msync");
+ udelay(200);
+ while (in_be32(&gur->ddrdllcr) != 0x81000100) {
+ setbits_be32(&gur->devdisr, 0x00010000);
+ for (i = 0; i < x; i++)
+ ;
+ clrbits_be32(&gur->devdisr, 0x00010000);
+ x++;
+ }
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ /* Some boards also have sdram on the lbc */
+ sdram_init();
+
+ puts("DDR: ");
+ return dram_size;
+}
+#endif
+
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index fcef40c5b8beb55add7b72ae81d280ae56f3dafc..10fcd243f71346c33744fcdba0f3962f648fa476 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -9,6 +9,16 @@
#include <common.h>
#include <asm/fsl_lbc.h>
+#ifdef CONFIG_MPC85xx
+/* Boards should provide their own version of this if they use lbc sdram */
+void __sdram_init(void)
+{
+ /* Do nothing */
+}
+void sdram_init(void) __attribute__((weak, alias("__sdram_init")));
+#endif
+
+
void print_lbc_regs(void)
{
int i;
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 17d4b319bcb4ecd603b7423e2321ac982c542ae2..8ceae18457259f412586263d0f5b7a8cc2c908ef 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -214,6 +214,19 @@ typedef struct memctl_options_s {
extern phys_size_t fsl_ddr_sdram(void);
+/*
+ * The 85xx boards have a common prototype for fixed_sdram so put the
+ * declaration here.
+ */
+#ifdef CONFIG_MPC85xx
+extern phys_size_t fixed_sdram(void);
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+
typedef struct fixed_ddr_parm{
int min_freq;
int max_freq;
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 82d24ab13f861cf8c6ebcc84cd35fd2f09d7ff27..fcf3371f59076a1c5daedd6f01745fbb5436ff79 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -16,6 +16,10 @@
#include <config.h>
#include <common.h>
+#ifdef CONFIG_MPC85xx
+void sdram_init(void);
+#endif
+
/* BR - Base Registers
*/
#define BR0 0x5000 /* Register offset to immr */
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index bd80cb776529e9bc036b93a50f3f724f907cfefe..58dc564eea69f389bd95a652e76045a2a2c87743 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -42,8 +42,6 @@
#include "../common/sgmii_riser.h"
-phys_size_t fixed_sdram(void);
-
int board_early_init_f (void)
{
#ifdef CONFIG_MMC
@@ -98,25 +96,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....");
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#if !defined(CONFIG_SPD_EEPROM)
/*
* Fixed sdram init -- doesn't use serial presence detect.
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index d354a26f69a45f3fae22215df3ec12e3a5e535f9..deab811bdd2ab3df54f7dc52a6fd17e15f996f6f 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram(void);
int checkboard (void)
{
@@ -61,54 +59,6 @@ int checkboard (void)
return 0;
}
-
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
-
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- /*
- * Initialize SDRAM.
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-
/*
* Initialize Local Bus
*/
@@ -232,7 +182,7 @@ sdram_init(void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
-long int fixed_sdram (void)
+phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
index a9925d54277bc503fcd8b070641152a965016e8f..adcc0ade0ab27aa5cd1295e92853c54525f1d046 100644
--- a/board/freescale/mpc8540ads/tlb.c
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: 128M DDR
- * 0x00000000 64M DDR System memory
- * 0x04000000 64M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_64M, 1),
-#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 59ec60446e91acda15112254ce866f6a83e37793..59df2bdb3932dc9f6b7bfbe3781c624fd67d712d 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
-void sdram_init(void);
/*
* I/O Port configuration table
@@ -242,48 +241,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 2b6900c081ba7356175e4e2d15e188caca6732eb..caea2f4d9ff90f93bf6f14f395f2b222ad0cbe23 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -68,23 +68,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
- dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index ebeb897490e66a54846db2ffe098dbacfe3ed790..a4a35fa3bfe3ab6186796fbe8b3b3d16865119bd 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -42,7 +42,6 @@
DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
-void sdram_init(void);
int checkboard (void)
{
@@ -75,43 +74,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index edaba26f5335fdb26d504d1be79fec5844d155eb..5fe7f13981a2c775322e4c83db464f8f1b675a3f 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
-void sdram_init(void);
/*
* I/O Port configuration table
@@ -240,50 +239,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 2ae0459fec042d0e8d08bff790c29db681336ab5..49701efda8fc2ce593b7d59f9bea2bc7a057a04b 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram(void);
/*
@@ -266,54 +264,6 @@ int checkboard (void)
return 0;
}
-
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
-
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- /*
- * Initialize SDRAM.
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-
/*
* Initialize Local Bus
*/
@@ -437,7 +387,7 @@ sdram_init(void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
-long int fixed_sdram (void)
+phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
index a9925d54277bc503fcd8b070641152a965016e8f..adcc0ade0ab27aa5cd1295e92853c54525f1d046 100644
--- a/board/freescale/mpc8560ads/tlb.c
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: 128M DDR
- * 0x00000000 64M DDR System memory
- * 0x04000000 64M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_64M, 1),
-#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 71cfbf0f375e52499380fb241735bbb6fc2da62d..85885fc4fe897c064089cedd218f802df30d326f 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -101,7 +101,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
};
void local_bus_init(void);
-void sdram_init(void);
int board_early_init_f (void)
{
@@ -138,43 +137,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 9700b8c6e8a44641e72a678dce989d6e360b9c7b..07db16aa0c237047a084fc78d16c286325afc4c3 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -45,8 +45,6 @@
#include "../common/pq-mds-pib.h"
#endif
-phys_size_t fixed_sdram(void);
-
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDC */
{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
@@ -245,40 +243,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
- volatile ccsr_gur_t *gur =
- (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- out_be32(&gur->ddrdllcr, 0x81000000);
- udelay(200);
-#endif
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index c217c278ea90c5bc09d52523b24b0b03bff3d74e..c69dfe4cc4e780bd8c455992c85da61212cdae35 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -39,8 +39,6 @@
#include "../common/sgmii_riser.h"
-long int fixed_sdram(void);
-
int checkboard (void)
{
u8 vboot;
@@ -74,23 +72,6 @@ int checkboard (void)
return 0;
}
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....");
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
#if !defined(CONFIG_SPD_EEPROM)
/*
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 7cb549b1bfb6a5932bb473b955f5b0749ae311c1..e3e830066be646829f21a1d169dfab49dec2149b 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -76,19 +76,6 @@ int checkboard(void)
return 0;
}
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....\n");
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 15b46b0da153b6b2fd957ce7a578203304d5c790..e54fde25309ed393d26ec10777874582bb7ab50e 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
return ddr_size;
}
-
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- dram_size = fixed_sdram();
- set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts("DDR: ");
- return dram_size;
-}
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 07b08014df1ad0306fdb65beb3a9a4d9089aafa8..40589da117e751148158117b98c1f71bfc43f8ab 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -44,8 +44,6 @@
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t fixed_sdram(void);
-
int checkboard(void)
{
u8 sw;
@@ -70,31 +68,6 @@ int checkboard(void)
return 0;
}
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....");
-
-#ifdef CONFIG_DDR_SPD
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- dram_size,
- LAW_TRGT_IF_DDR) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#if !defined(CONFIG_DDR_SPD)
/*
* Fixed sdram init -- doesn't use serial presence detect.
@@ -170,6 +143,13 @@ phys_size_t fixed_sdram(void)
udelay(500);
#endif
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
+ LAW_TRGT_IF_DDR) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ };
+
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 06c1eea37792bd0fbb21585ef93da81327bcb8da..1bce6fa3f319e8245f946fb24cc0eb3743270a6d 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -43,8 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram (void);
int board_early_init_f (void)
{
@@ -69,47 +67,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- out_be32(&gur->ddrdllcr, 0x81000000);
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram ();
-#endif
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
@@ -268,7 +225,7 @@ testdram(void)
* fixed_sdram init -- doesn't use serial presence detect.
* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
************************************************************************/
-long int fixed_sdram (void)
+phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 38bdeb37c3009bcdc44d65ec6dc8ea95e8621d45..bb4c05210cc8f5753299c46d93b1fb07ab77e05c 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 1, BOOKE_PAGESZ_1G, 1),
/*
- * TLB 2: 256M Cacheable, non-guarded
- * 0x0 256M DDR SDRAM
- */
-#if !defined(CONFIG_SPD_EEPROM)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-#endif
-
- /*
- * TLB 3: 64M Non-cacheable, guarded
+ * TLB 2: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 8M PCI1 IO
* 0xe2800000 8M PCIe IO
*/
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_64M, 1),
+ 0, 2, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 4: 64M Cacheable, non-guarded
+ * TLB 3: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 4, BOOKE_PAGESZ_64M, 1),
+ 0, 3, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 5: 64M Cacheable, non-guarded
+ * TLB 4: 64M Cacheable, non-guarded
* 0xf4000000 64M LBC SDRAM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_64M, 1),
+ 0, 4, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 6: 16M Cacheable, non-guarded
+ * TLB 5: 16M Cacheable, non-guarded
* 0xf8000000 1M 7-segment LED display
* 0xf8100000 1M User switches
* 0xf8300000 1M Board revision
@@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
+ 0, 5, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 7: 4M Non-cacheable, guarded
+ * TLB 6: 4M Non-cacheable, guarded
* 0xfb800000 4M 1st 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
+ 0, 6, BOOKE_PAGESZ_4M, 1),
/*
- * TLB 8: 4M Non-cacheable, guarded
+ * TLB 7: 4M Non-cacheable, guarded
* 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
CONFIG_SYS_ALT_FLASH + 0x400000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4M, 1),
+ 0, 7, BOOKE_PAGESZ_4M, 1),
};
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index 7bf81799e517c80cf0459b4549432c740f7895c2..c5fe92e06154cd694f08683cc7921b947919a305 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -38,8 +38,6 @@
#include <libfdt.h>
#include <fdt_support.h>
-long int fixed_sdram (void);
-
/*
* I/O Port configuration table
*
@@ -263,95 +261,6 @@ int checkboard (void)
}
-phys_size_t initdram (int board_type)
-{
- long dram_size = 0;
-
-#if 0
-#if !defined(CONFIG_RAM_AS_FLASH)
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- sys_info_t sysinfo;
- uint temp_lbcdll = 0;
-#endif
-#endif /* 0 */
-#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
-#if defined(CONFIG_DDR_DLL)
- uint temp_ddrdll = 0;
-
- /* Work around to stabilize DDR DLL */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
-#endif
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram ();
-#endif
-
-#if 0
-#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
- get_sys_info(&sysinfo);
- /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
- if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
- lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
- } else {
-#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
- lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
-#endif
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
- udelay(200);
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
- asm("sync;isync;msync");
- }
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
- asm("sync");
- (unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
- asm("sync");
- (unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
- asm("sync");
- (unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
- asm("sync");
- (unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
- asm("sync");
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- asm("sync");
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- asm("sync");
-#endif
-#endif
-
-#if defined(CONFIG_DDR_ECC)
- {
- /* Initialize all of memory for ECC, then
- * enable errors */
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
- dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
-
- /* Enable errors for ECC */
- ddr->err_disable = 0x00000000;
- asm("sync;isync;msync");
- }
-#endif
-
- return dram_size;
-}
-
-
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
@@ -390,7 +299,7 @@ int testdram (void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
-long int fixed_sdram (void)
+phys_size_t fixed_sdram(void)
{
#define CONFIG_SYS_DDR_CONTROL 0xc2000000
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index ef897b216e3548f699ed9da68b7914e0b677db88..c8235f4a9b4a29dd384dc8c8cf677ab879d27793 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -39,7 +39,7 @@
* so this should be extended for other future boards
* using this routine!
*/
-long int fixed_sdram(void)
+phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -77,19 +77,6 @@ long int fixed_sdram(void)
}
#endif
-phys_size_t initdram (int board_type)
-{
- long dram_size = 0;
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
- return dram_size;
-}
-
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
index 1ed340efe7ca41354524ce778a79ee1e3efd5aac..de22bf5e0af1c8bb54e7b274a967eab46eb422fc 100644
--- a/board/stx/stxgp3/stxgp3.c
+++ b/board/stx/stxgp3/stxgp3.c
@@ -40,8 +40,6 @@
#include <spd_sdram.h>
#include <miiphy.h>
-long int fixed_sdram (void);
-
/*
* I/O Port configuration table
*
@@ -277,36 +275,6 @@ show_activity(int flag)
next_led_update += (get_tbclk() / 4);
}
-phys_size_t
-initdram (int board_type)
-{
- long dram_size = 0;
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
-
- /* Work around to stabilize DDR DLL */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC)
- /* Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- return dram_size;
-}
-
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index 6cd28a34b9f4a3728a050ed52d3bcc95d2e7564b..83ffcd2b924e7b80c0622025a3138779ff01f6f0 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -41,8 +41,6 @@
#include <miiphy.h>
#include <netdev.h>
-long int fixed_sdram (void);
-
/*
* I/O Port configuration table
*
@@ -294,37 +292,6 @@ show_activity(int flag)
next_led_update += (get_tbclk() / 4);
}
-phys_size_t
-initdram (int board_type)
-{
- long dram_size = 0;
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
-
- /* Work around to stabilize DDR DLL */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC)
- /* Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- return dram_size;
-}
-
-
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 260cd1c6dd82ccee48b95bb326072ea8f6c619fd..b2d3185351605989dfcf06996457d8e30771eecc 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl)
return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
}
-phys_size_t initdram (int board_type)
-{
- phys_size_t dram_size = 0;
-
-#if defined(CONFIG_DDR_DLL)
- /*
- * This DLL-Override only used on TQM8540 and TQM8560
- */
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int i, x;
-
- x = 10;
-
- /*
- * Work around to stabilize DDR DLL
- */
- gur->ddrdllcr = 0x81000000;
- asm ("sync; isync; msync");
- udelay (200);
- while (gur->ddrdllcr != 0x81000100) {
- gur->devdisr = gur->devdisr | 0x00010000;
- asm ("sync; isync; msync");
- for (i = 0; i < x; i++)
- ;
- gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm ("sync; isync; msync");
- x++;
- }
- }
-#endif
-
- dram_size = fixed_sdram();
-
- return dram_size;
-}
-
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 75dd348aa529c7405580d6b288857b71438bd6a9..f9f8cc9a01e828de413ee66d4d6aa9ae1b7dd54d 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
-
-#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
- /*
- * TLB 7+8: 2G DDR, cache enabled
- * 0x00000000 2G DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_1G, 1),
-
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#else
- /*
- * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
- * 0x00000000 512M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
-#endif
#ifdef CONFIG_PCIE1
/*
* TLB 9: 16M Non-cacheable, guarded
@@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 8+9: 512M DDR, cache disabled (needed for memory test)
- * 0x00000000 512M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 9, BOOKE_PAGESZ_256M, 1),
-
#ifdef CONFIG_PCIE1
/*
* TLB 10: 16M Non-cacheable, guarded
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index 7604f626bbc98f668c5f9eb4117dd76fb2bbca4f..39d105fcdd01cd2084cfbc3a8c660036c0c0a7d6 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o
-COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
-COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o
COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c
deleted file mode 100644
index 81ee70d5a149f66a0a5a8f24637b14e8021b22fe..0000000000000000000000000000000000000000
--- a/board/xes/common/fsl_8xxx_ddr.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/mmu.h>
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = fsl_ddr_sdram();
-
-#ifdef CONFIG_MPC85xx
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /* Initialize and enable DDR ECC */
- ddr_enable_ecc(dram_size);
-#endif
-
- return dram_size;
-}
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index 0f7fa6c43abe3767bb2dcb8bcc04bdc2b6590632..572a9080047eee15d0a273ab6fac341bbf093fb6 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <fdt_support.h>
@@ -71,6 +72,18 @@ int board_early_init_r(void)
return 0;
}
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = fsl_ddr_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /* Initialize and enable DDR ECC */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ return dram_size;
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 890d6d9d4ccf6f0e0b67aa2c0981d5fddecbe12c..febe95da89c36767a11d1c655c6a31e41959f71a 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -147,6 +147,10 @@
* DDR Setup
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#if defined(CONFIG_TQM_BIGFLASH) || \
+ (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
+#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
+#endif
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_TQM8548_AG
#define CONFIG_VERY_BIG_RAM