diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 0852d8dc53cee784773b05bf70fcfc91086ffbad..1a9ce2720acd4b25537d3163860d2f737084ab04 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -119,9 +119,6 @@
vccio-supply = <&sys_3v3_reg>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
/* SW1: +V1.35_VDDIO_DDR */
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v35";
diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index c1a15bb4b3ce56517dd0eb85ac5ecc040291323e..f5fbbe849e26eee624a4796678a7fe0e3273ec7b 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -102,9 +102,6 @@
vccio-supply = <&vdd_5v_in_reg>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v2";
regulator-min-microvolt = <1200000>;
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
index a54425692b5717b7bf237a7a39b6c994714587ed..62947bf99c84dd38ccd7269fc2ba9e582fc24b17 100644
--- a/arch/arm/include/asm/arch-tegra124/flow.h
+++ b/arch/arm/include/asm/arch-tegra124/flow.h
@@ -29,7 +29,7 @@ struct flow_ctlr {
u32 flow_dbg_cnt0; /* offset 0x48 */
u32 flow_dbg_cnt1; /* offset 0x4c */
u32 flow_dbg_qual; /* offset 0x50 */
- u32 flow_ctlr_spare; /* offset 0x54 */
+ u32 flow_ctrl_spare; /* offset 0x54 */
u32 ram_repair_cluster1;/* offset 0x58 */
};
@@ -48,10 +48,8 @@ struct flow_ctlr {
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_PWR_OFF_STS (1 << 16)
-/* RAM_REPAIR, 0x40, 0x58 */
-enum {
- RAM_REPAIR_REQ = 0x1 << 0,
- RAM_REPAIR_STS = 0x1 << 1,
-};
+#define RAM_REPAIR_REQ BIT(0)
+#define RAM_REPAIR_STS BIT(1)
+#define RAM_REPAIR_BYPASS_EN BIT(2)
#endif /* _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h
index 71df5a9e253809e9baa95afa29724972ea447e16..183b00a08719fb8a9c024303d5f8ec086d5f545f 100644
--- a/arch/arm/include/asm/proc-armv/ptrace.h
+++ b/arch/arm/include/asm/proc-armv/ptrace.h
@@ -37,6 +37,7 @@ struct pt_regs {
#define FIQ_MODE 0x11
#define IRQ_MODE 0x12
#define SVC_MODE 0x13
+#define MON_MODE 0x16
#define ABT_MODE 0x17
#define HYP_MODE 0x1a
#define UND_MODE 0x1b
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index 825fe1eefb3cc04610f1d5321e837a18258d31df..246f3c7cb84a1a0ef57ec0e956099c45f223b0f5 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -67,6 +67,8 @@ init_psci_node:
psci_ver = sec_firmware_support_psci_version();
#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
+#elif defined(CONFIG_ARMV7_PSCI_0_2)
+ psci_ver = ARM_PSCI_VER_0_2;
#endif
if (psci_ver >= ARM_PSCI_VER_1_0) {
tmp = fdt_setprop_string(fdt, nodeoff,
@@ -114,6 +116,10 @@ init_psci_node:
if (tmp)
return tmp;
+ tmp = fdt_setprop_string(fdt, nodeoff, "status", "okay");
+ if (tmp)
+ return tmp;
+
#endif
return 0;
}
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 25da771607b7b0d497ab56f64add72586619accd..5ecadf705e7ebaffa35a2c97f1a2df4532a0b3eb 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -249,6 +249,10 @@ static ulong carveout_size(void)
{
#ifdef CONFIG_ARM64
return SZ_512M;
+#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
+ // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
+ // from BASE to 4GB, not BASE to BASE+SIZE.
+ return (0 - CONFIG_ARMV7_SECURE_BASE);
#else
return 0;
#endif
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index d32d559f13ad62b594d367127709ccf8b1d5826a..e45f0961b242cdd92c344bcd186583dc80131f5b 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -8,7 +8,7 @@
#include <asm/io.h>
#include <asm/types.h>
-#include <asm/arch/flow.h>
+
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
@@ -74,29 +74,11 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id)
return 0;
}
-static void tegra_powergate_ram_repair(void)
-{
-#ifdef CONFIG_TEGRA124
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
- /* Request RAM repair for cluster 0 and wait until complete */
- setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
- ;
-
- /* Same for cluster 1 */
- setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
- ;
-#endif
-}
-
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph)
{
int err;
- tegra_powergate_ram_repair();
reset_set_enable(periph, 1);
err = tegra_powergate_power_on(id);
diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c
index 204d6e95395d9c423a0d094f9f3ea4442329e19b..992c0beb04dce15d8b6b951581a25b2e615c9ca0 100644
--- a/arch/arm/mach-tegra/tegra124/cpu.c
+++ b/arch/arm/mach-tegra/tegra124/cpu.c
@@ -104,6 +104,43 @@ static void remove_cpu_resets(void)
writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
}
+static void tegra124_ram_repair(void)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ u32 ram_repair_timeout; /*usec*/
+ u32 val;
+
+ /*
+ * Request the Flow Controller perform RAM repair whenever it turns on
+ * a power rail that requires RAM repair.
+ */
+ clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN);
+
+ /* Request SW trigerred RAM repair by setting req bit */
+ /* cluster 0 */
+ setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+ /* Wait for completion (status == 0) */
+ ram_repair_timeout = 500;
+ do {
+ udelay(1);
+ val = readl(&flow->ram_repair);
+ } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
+ if (!ram_repair_timeout)
+ debug("Ram Repair cluster0 failed\n");
+
+ /* cluster 1 */
+ setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+ /* Wait for completion (status == 0) */
+ ram_repair_timeout = 500;
+ do {
+ udelay(1);
+ val = readl(&flow->ram_repair_cluster1);
+ } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
+
+ if (!ram_repair_timeout)
+ debug("Ram Repair cluster1 failed\n");
+}
+
/**
* Tegra124 requires some special clock initialization, including setting up
* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
@@ -254,10 +291,11 @@ void start_cpu(u32 reset_vector)
&pmc->pmc_pwrgate_timer_mult);
enable_cpu_power_rail();
+ powerup_cpus();
+ tegra124_ram_repair();
enable_cpu_clocks();
clock_enable_coresight(1);
- remove_cpu_resets();
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
- powerup_cpus();
+ remove_cpu_resets();
debug("%s exit, should continue @ reset_vector\n", __func__);
}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 1aebe174218dafe1cc0967a0c0ffd1dd177b393f..7ced4099f22827961fe4a5aaced87623914ddf21 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -51,6 +51,7 @@ CONFIG_ARMADA100
CONFIG_ARMADA100_FEC
CONFIG_ARMADA168
CONFIG_ARMADA_39X
+CONFIG_ARMV7_PSCI_0_2
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE