From 5b2052e5f5fcce5dbd4d2750a29c0e45bce806e7 Mon Sep 17 00:00:00 2001 From: Eugene O'Brien <eugene.obrien@advantechamt.com> Date: Fri, 11 Apr 2008 10:00:35 -0400 Subject: [PATCH] ppc4xx: Fix power mgt definitions for PPC440 Corrected DCR addresses of PPC440EP power management registers. Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> --- include/ppc440.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/include/ppc440.h b/include/ppc440.h index 642d1ded762..bb39ad63175 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1731,17 +1731,10 @@ #else #define CNTRL_DCR_BASE 0x0b0 #endif -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ -#else -#define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */ -#define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */ -#define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */ -#endif #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ -- GitLab