diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 442d373e0954ed9b3a3b3cf1d7935b32bd2dee30..d2901de6d5888bf943fd03cf891ae204b0195834 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -26,7 +26,7 @@ bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
 	if (priv->config == PIRQ_VIA_PCI)
 		dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
 	else
-		pirq = readb(priv->ibase + LINK_N2V(link, base));
+		pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base));
 
 	pirq &= 0xf;
 
@@ -56,7 +56,7 @@ void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
 	if (priv->config == PIRQ_VIA_PCI)
 		dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
 	else
-		writeb(irq, priv->ibase + LINK_N2V(link, base));
+		writeb(irq, (uintptr_t)priv->ibase + LINK_N2V(link, base));
 }
 
 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
@@ -234,7 +234,7 @@ static void irq_enable_sci(struct udevice *dev)
 		if (priv->config == PIRQ_VIA_PCI)
 			dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
 		else
-			writel(0, priv->ibase + priv->actl_addr);
+			writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
 	}
 }
 
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 85e24813851130fc99cc83eb8b3c419fb0d007d9..7153eb21f57e5e71785f8b4a80da154d8266dba4 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -47,7 +47,7 @@ static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
 static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
 {
 	/* the DMA address register is big endian */
-	outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
+	outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
 
 	while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
 		__asm__ __volatile__ ("pause");