diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 0cc6e0323f2e8331a4ff9ef5daa7b5023ad907f3..15b7b231eea524dcce53f0788efcdf91e3aee6ac 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
  * (C) Copyright 2002, 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -44,21 +44,17 @@ int checkcpu (void)
 	uint major, minor;
 	struct cpu_type *cpu;
 	char buf1[32], buf2[32];
-#ifdef CONFIG_DDR_CLK_FREQ
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_CORENET
-	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
-		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
-#else
+#ifdef CONFIG_DDR_CLK_FREQ
 	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
 		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#endif
 #else
 #ifdef CONFIG_FSL_CORENET
-	u32 ddr_sync = 0;
+	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
 #else
 	u32 ddr_ratio = 0;
-#endif
+#endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
 	int i;
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 268edbc5b7368fc6a4dda852ade6e2491f79efcb..8132115fca6e9f455629844c77528490ad6f7e7a 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
@@ -71,22 +71,30 @@ void get_sys_info (sys_info_t * sysInfo)
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
 	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+	uint ratio[4];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	uint mem_pll_rat;
 
 	sysInfo->freqSystemBus = sysclk;
 	sysInfo->freqDDRBus = sysclk;
-	freqCC_PLL[0] = sysclk;
-	freqCC_PLL[1] = sysclk;
-	freqCC_PLL[2] = sysclk;
-	freqCC_PLL[3] = sysclk;
 
 	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
-	freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
-	freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
-	freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
-	freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+	if (mem_pll_rat > 2)
+		sysInfo->freqDDRBus *= mem_pll_rat;
+	else
+		sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
 
+	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
+	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
+	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
+	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+	for (i = 0; i < 4; i++) {
+		if (ratio[i] > 4)
+			freqCC_PLL[i] = sysclk * ratio[i];
+		else
+			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
+	}
 	rcw_tmp = in_be32(&gur->rcwsr[3]);
 	for (i = 0; i < cpu_numcores(); i++) {
 		u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 957ad76a7964d09728456260a3a5c60f1885f154..dd28e3239acca346923839fd8e10f09532ae7cca 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1697,8 +1697,8 @@ typedef struct ccsr_gur {
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
-#define FSL_CORENET_RCWSR5_DDR_SYNC		0x00008000
-#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		15
+#define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000