diff --git a/arch/Kconfig b/arch/Kconfig
index 207c778d13c45cc721fceeaa5dfe46abab9c59df..9be15383bb004c5aef66d92c8069726b8454cf42 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -64,6 +64,9 @@ config NIOS2
select HAVE_GENERIC_BOARD
select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
+ select OF_CONTROL
+ select DM
+ select CPU
config OPENRISC
bool "OpenRISC architecture"
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index 39ae97221c2a95f2b2395f4ac74318b9e6203f70..34eb7bd68320b53c2d45588d0829181029745601 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -6,7 +6,9 @@
*/
#include <common.h>
-#include <asm/nios2.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
#include <asm/cache.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,10 +53,92 @@ void dcache_disable(void)
flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
}
-int arch_cpu_init(void)
+int arch_cpu_init_dm(void)
{
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_CPU, &dev);
+ if (ret)
+ return ret;
+ if (!dev)
+ return -ENODEV;
+
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
+
+static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size)
+{
+ const char *cpu_name = "Nios-II";
+
+ if (size < strlen(cpu_name))
+ return -ENOSPC;
+ strcpy(buf, cpu_name);
+
+ return 0;
+}
+
+static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ info->cpu_freq = gd->cpu_clk;
+ info->features = (1 << CPU_FEAT_L1_CACHE) |
+ (gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0);
+
+ return 0;
+}
+
+static int altera_nios2_get_count(struct udevice *dev)
+{
+ return 1;
+}
+
+static int altera_nios2_probe(struct udevice *dev)
+{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+
+ gd->cpu_clk = fdtdec_get_int(blob, node,
+ "clock-frequency", 0);
+ gd->arch.dcache_line_size = fdtdec_get_int(blob, node,
+ "dcache-line-size", 0);
+ gd->arch.icache_line_size = fdtdec_get_int(blob, node,
+ "icache-line-size", 0);
+ gd->arch.dcache_size = fdtdec_get_int(blob, node,
+ "dcache-size", 0);
+ gd->arch.icache_size = fdtdec_get_int(blob, node,
+ "icache-size", 0);
+ gd->arch.reset_addr = fdtdec_get_int(blob, node,
+ "altr,reset-addr", 0);
+ gd->arch.exception_addr = fdtdec_get_int(blob, node,
+ "altr,exception-addr", 0);
+ gd->arch.has_initda = fdtdec_get_int(blob, node,
+ "altr,has-initda", 0);
+ gd->arch.has_mmu = fdtdec_get_int(blob, node,
+ "altr,has-mmu", 0);
+ gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000;
+
+ return 0;
+}
+
+static const struct cpu_ops altera_nios2_ops = {
+ .get_desc = altera_nios2_get_desc,
+ .get_info = altera_nios2_get_info,
+ .get_count = altera_nios2_get_count,
+};
+
+static const struct udevice_id altera_nios2_ids[] = {
+ { .compatible = "altr,nios2-1.0" },
+ { .compatible = "altr,nios2-1.1" },
+ { }
+};
+
+U_BOOT_DRIVER(altera_nios2) = {
+ .name = "altera_nios2",
+ .id = UCLASS_CPU,
+ .of_match = altera_nios2_ids,
+ .probe = altera_nios2_probe,
+ .ops = &altera_nios2_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h
index 580b0199bb8563d94852a22c65d7a75c5b118bb0..d6a2cfab4f9e58444dd4fcfc21248e5b8df16435 100644
--- a/arch/nios2/include/asm/global_data.h
+++ b/arch/nios2/include/asm/global_data.h
@@ -9,6 +9,15 @@
/* Architecture-specific global data */
struct arch_global_data {
+ u32 dcache_line_size;
+ u32 icache_line_size;
+ u32 dcache_size;
+ u32 icache_size;
+ u32 reset_addr;
+ u32 exception_addr;
+ int has_initda;
+ int has_mmu;
+ u32 io_region_base;
};
#include <asm-generic/global_data.h>
diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig
index ad7227265ae6afeddef669e13004d897fb3d4b3d..707ee3363fbd9ca41e3a690710013720e193ec4e 100644
--- a/configs/nios2-generic_defconfig
+++ b/configs/nios2-generic_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_GPIO=y
CONFIG_TARGET_NIOS2_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
@@ -13,9 +14,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
-CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
CONFIG_ALTERA_PIO=y
CONFIG_ALTERA_JTAG_UART=y
CONFIG_ALTERA_JTAG_UART_BYPASS=y
diff --git a/doc/device-tree-bindings/cpu/nios2.txt b/doc/device-tree-bindings/cpu/nios2.txt
new file mode 100644
index 0000000000000000000000000000000000000000..0ed2f44bcf269ab0ae796b8ff783bbc1a818b886
--- /dev/null
+++ b/doc/device-tree-bindings/cpu/nios2.txt
@@ -0,0 +1,54 @@
+* Nios II Processor Binding
+
+This binding specifies what properties available in the device tree
+representation of a Nios II Processor Core.
+
+Users can use sopc2dts tool for generating device tree sources (dts) from a
+Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
+
+Required properties:
+
+- compatible: Compatible property value should be "altr,nios2-1.0" or
+ "altr,nios2-1.1".
+- reg: Contains CPU index.
+- clock-frequency: Contains the clock frequency for CPU, in Hz.
+- dcache-line-size: Contains data cache line size.
+- icache-line-size: Contains instruction line size.
+- dcache-size: Contains data cache size.
+- icache-size: Contains instruction cache size.
+- altr,reset-addr: Specifies CPU reset address
+- altr,exception-addr: Specifies CPU exception address
+
+Optional properties:
+- altr,has-initda: Specifies CPU support initda instruction, should be 1.
+- altr,has-mmu: Specifies CPU support MMU support.
+- altr,has-mul: Specifies CPU hardware multipy support.
+- altr,has-div: Specifies CPU hardware divide support
+- altr,implementation: Nios II core implementation, this should be "fast";
+
+Example:
+
+cpu@0x0 {
+ device_type = "cpu";
+ compatible = "altr,nios2-1.0";
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clock-frequency = <125000000>;
+ dcache-line-size = <32>;
+ icache-line-size = <32>;
+ dcache-size = <32768>;
+ icache-size = <32768>;
+ altr,implementation = "fast";
+ altr,pid-num-bits = <8>;
+ altr,tlb-num-ways = <16>;
+ altr,tlb-num-entries = <128>;
+ altr,tlb-ptr-sz = <7>;
+ altr,has-div = <1>;
+ altr,has-mul = <1>;
+ altr,reset-addr = <0xc2800000>;
+ altr,fast-tlb-miss-addr = <0xc7fff400>;
+ altr,exception-addr = <0xd0000020>;
+ altr,has-initda = <1>;
+ altr,has-mmu = <1>;
+};