diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt
index 034146f5f802ca60cbf24f8f24f4b36c8dd1d5cd..268220964aab84d7c7ff91282670eb6713701195 100644
--- a/doc/device-tree-bindings/net/ti,dp83867.txt
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -12,8 +12,10 @@ Required properties:
 		compensate for the board being designed with the lanes swapped.
 	- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
 		TX/RX lanes.
-	- ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
-		for applicable values
+	- ti,clk-output-sel - Muxing option for CLK_OUT pin.  See dt-bindings/net/ti-dp83867.h
+			      for applicable values.  The CLK_OUT pin can also
+			      be disabled by this property.  When omitted, the
+			      PHY's default will be left as is.
 
 Default child nodes are standard Ethernet PHY device
 nodes as described in doc/devicetree/bindings/net/ethernet.txt
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
index 85d08f69746e75e228503db2c697a58bb6050289..cde5aa7e27d0c39e0f6e5f485d012548f5e75035 100644
--- a/include/dt-bindings/net/ti-dp83867.h
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -45,5 +45,6 @@
 #define DP83867_CLK_O_SEL_CHN_C_TCLK		0xA
 #define DP83867_CLK_O_SEL_CHN_D_TCLK		0xB
 #define DP83867_CLK_O_SEL_REF_CLK		0xC
-
+/* Special flag to indicate clock should be off */
+#define DP83867_CLK_O_SEL_OFF			0xFFFFFFFF
 #endif