A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.

Issue:
Wrong base address is assigned to MDIO interface during probe.

Fix:
Get MDIO address from PHY handler parent base address.

This should be refined in the future when MDIO driver is implemented.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>