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Michal Simek authored
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which means FORCE_LINK_GOOD is already setup. Origin code was doing write but the new code is doing read/modify/write and keep this bit untouched. That's why ethernet stop to work. The patch is cleaning this bit when PHYCR value is composed. Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards. Fixes: 37d6265f ("net: phy: dp83867: refactor rgmii configuration") Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Reviewed-by:
Grygorii Strashko <grygorii.strashko@ti.com>
Michal Simek authoredOn Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which means FORCE_LINK_GOOD is already setup. Origin code was doing write but the new code is doing read/modify/write and keep this bit untouched. That's why ethernet stop to work. The patch is cleaning this bit when PHYCR value is composed. Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards. Fixes: 37d6265f ("net: phy: dp83867: refactor rgmii configuration") Signed-off-by:
