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    7b37a9c7
    ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715 · 7b37a9c7
    Nishanth Menon authored
    As recommended by Arm in [1], IBE[2] has to be enabled unconditionally
    for BPIALL to be functional on Cortex-A8 processors. Provide a config
    option for platforms to enable this option based on impact analysis
    for products.
    
    NOTE: This patch in itself is NOT the final solution, this requires:
    a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
       provide direct access to ACR register.
    b) Operating Systems such as Linux to provide adequate workaround in the right
       locations.
    c) This workaround applies to only the boot processor. It is important
       to apply workaround as necessary (context-save-restore) around low
       power context loss OR additional processors as necessary in either
       firmware support OR elsewhere in OS.
    
    [1] https://developer.arm.com/support/security-update
    [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html
    
    
    
    Cc: Marc Zyngier <marc.zyngier@arm.com>
    Cc: Russell King <linux@arm.linux.org.uk>
    Cc: Tony Lindgren <tony@atomide.com>
    Cc: Robin Murphy <robin.murphy@arm.com>
    Cc: Florian Fainelli <f.fainelli@gmail.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Will Deacon <will.deacon@arm.com>
    Cc: Christoffer Dall <christoffer.dall@linaro.org>
    Cc: Andre Przywara <Andre.Przywara@arm.com>
    Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Cc: Tom Rini <trini@konsulko.com>
    Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
    
    Signed-off-by: default avatarNishanth Menon <nm@ti.com>
    Tested-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
    7b37a9c7
    History
    ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715
    Nishanth Menon authored
    As recommended by Arm in [1], IBE[2] has to be enabled unconditionally
    for BPIALL to be functional on Cortex-A8 processors. Provide a config
    option for platforms to enable this option based on impact analysis
    for products.
    
    NOTE: This patch in itself is NOT the final solution, this requires:
    a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
       provide direct access to ACR register.
    b) Operating Systems such as Linux to provide adequate workaround in the right
       locations.
    c) This workaround applies to only the boot processor. It is important
       to apply workaround as necessary (context-save-restore) around low
       power context loss OR additional processors as necessary in either
       firmware support OR elsewhere in OS.
    
    [1] https://developer.arm.com/support/security-update
    [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html
    
    
    
    Cc: Marc Zyngier <marc.zyngier@arm.com>
    Cc: Russell King <linux@arm.linux.org.uk>
    Cc: Tony Lindgren <tony@atomide.com>
    Cc: Robin Murphy <robin.murphy@arm.com>
    Cc: Florian Fainelli <f.fainelli@gmail.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Will Deacon <will.deacon@arm.com>
    Cc: Christoffer Dall <christoffer.dall@linaro.org>
    Cc: Andre Przywara <Andre.Przywara@arm.com>
    Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Cc: Tom Rini <trini@konsulko.com>
    Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
    
    Signed-off-by: default avatarNishanth Menon <nm@ti.com>
    Tested-by: default avatarFabio Estevam <fabio.estevam@nxp.com>