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Commit 1ba62f10 authored by York Sun's avatar York Sun Committed by Andy Fleming
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powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards 


P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.

Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent 119a55f9
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