mx6sxsabresd: Fix Ethernet PHY reset sequence

Since commit 59370f3f ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.

This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.

Fix this by calling enable_fec_anatop_clock() earlier and also
by adding a 10ms reset delay as recommended in the AR8031 datasheet.

Suggested-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>