clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()

Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>

drivers/clk/imx/clk-pllv3.c

@@ -121,10 +121,16 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
 {
 	struct clk_pllv3 *pll = to_clk_pllv3(clk);
 	unsigned long parent_rate = clk_get_parent_rate(clk);
-	unsigned long min_rate = parent_rate * 54 / 2;
-	unsigned long max_rate = parent_rate * 108 / 2;
+	unsigned long min_rate;
+	unsigned long max_rate;
 	u32 val, div;
 
+	if (parent_rate == 0)
+		return -EINVAL;
+
+	min_rate = parent_rate * 54 / 2;
+	max_rate = parent_rate * 108 / 2;
+
 	if (rate < min_rate || rate > max_rate)
 		return -EINVAL;