riscv: cache: Implement i/dcache [status, enable, disable]
AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.
This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.
This approach also provide the expansion when the
vender specific features are going to join in.
Signed-off-by: 
Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
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- arch/riscv/Kconfig 6 additions, 0 deletionsarch/riscv/Kconfig
- arch/riscv/cpu/ax25/Kconfig 7 additions, 0 deletionsarch/riscv/cpu/ax25/Kconfig
- arch/riscv/cpu/ax25/Makefile 1 addition, 0 deletionsarch/riscv/cpu/ax25/Makefile
- arch/riscv/cpu/ax25/cache.c 95 additions, 0 deletionsarch/riscv/cpu/ax25/cache.c
- arch/riscv/cpu/ax25/cpu.c 4 additions, 0 deletionsarch/riscv/cpu/ax25/cpu.c
- arch/riscv/cpu/qemu/cpu.c 1 addition, 1 deletionarch/riscv/cpu/qemu/cpu.c
- arch/riscv/cpu/start.S 6 additions, 0 deletionsarch/riscv/cpu/start.S
- arch/riscv/include/asm/cache.h 3 additions, 0 deletionsarch/riscv/include/asm/cache.h
- arch/riscv/lib/cache.c 23 additions, 9 deletionsarch/riscv/lib/cache.c
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