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Commit 52923c6d authored by Rick Chen's avatar Rick Chen Committed by Andes
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riscv: cache: Implement i/dcache [status, enable, disable]


AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.

This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.

This approach also provide the expansion when the
vender specific features are going to join in.

Signed-off-by: default avatarRick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
parent bae2d725
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