ARM: socfpga: Zap unused reset code

Remove code from the reset manager that is never called.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h

@@ -10,10 +10,7 @@
 
 void socfpga_watchdog_disable(void);
 void socfpga_reset_deassert_noc_ddr_scheduler(void);
-int socfpga_is_wdt_in_reset(void);
-void socfpga_emac_manage_reset(ulong emacbase, u32 state);
 int socfpga_reset_deassert_bridges_handoff(void);
-void socfpga_reset_assert_fpga_connected_peripherals(void);
 void socfpga_reset_deassert_osc1wd0(void);
 int socfpga_bridges_reset(void);
 

arch/arm/mach-socfpga/reset_manager_arria10.c

@@ -20,59 +20,6 @@ static const struct socfpga_reset_manager *reset_manager_base =
 static const struct socfpga_system_manager *sysmgr_regs =
 		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \
-	ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \
-	ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \
-	ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \
-	ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
-	ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
-
-static const u32 per0fpgamasks[] = {
-	ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
-	ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
-	ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
-	ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
-	ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
-	ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
-	0, /* i2c0 per1mod */
-	0, /* i2c1 per1mod */
-	0, /* i2c0_emac */
-	0, /* i2c1_emac */
-	0, /* i2c2_emac */
-	ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
-	ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
-	ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
-	ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
-	ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
-	ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
-	ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
-	ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
-	ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
-	ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
-	0, /* uart0 per1mod */
-	0, /* uart1 per1mod */
-};
-
-static const u32 per1fpgamasks[] = {
-	0, /* emac0 per0mod */
-	0, /* emac1 per0mod */
-	0, /* emac2 per0mod */
-	ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
-	ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
-	ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
-	ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
-	ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
-	0, /* nand per0mod */
-	0, /* qspi per0mod */
-	0, /* sdmmc per0mod */
-	0, /* spim0 per0mod */
-	0, /* spim1 per0mod */
-	0, /* spis0 per0mod */
-	0, /* spis1 per0mod */
-	ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
-	ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
-};
-
 struct bridge_cfg {
 	int compat_id;
 	u32  mask_noc;
@@ -127,56 +74,6 @@ void socfpga_reset_deassert_noc_ddr_scheduler(void)
 		     ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
 }
 
-/* Check whether Watchdog in reset state? */
-int socfpga_is_wdt_in_reset(void)
-{
-	u32 val;
-
-	val = readl(&reset_manager_base->per1modrst);
-	val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
-
-	/* return 0x1 if watchdog in reset */
-	return val;
-}
-
-/* emacbase: base address of emac to enable/disable reset
- * state: 0 - disable reset, !0 - enable reset
- */
-void socfpga_emac_manage_reset(ulong emacbase, u32 state)
-{
-	ulong eccmask;
-	ulong emacmask;
-
-	switch (emacbase) {
-	case SOCFPGA_EMAC0_ADDRESS:
-		eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK;
-		emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK;
-		break;
-	case SOCFPGA_EMAC1_ADDRESS:
-		eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK;
-		emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK;
-		break;
-	case SOCFPGA_EMAC2_ADDRESS:
-		eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK;
-		emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK;
-		break;
-	default:
-		pr_err("emac base address unexpected! %lx", emacbase);
-		hang();
-		break;
-	}
-
-	if (state) {
-		/* Enable ECC OCP first */
-		setbits_le32(&reset_manager_base->per0modrst, eccmask);
-		setbits_le32(&reset_manager_base->per0modrst, emacmask);
-	} else {
-		/* Disable ECC OCP first */
-		clrbits_le32(&reset_manager_base->per0modrst, emacmask);
-		clrbits_le32(&reset_manager_base->per0modrst, eccmask);
-	}
-}
-
 static int get_bridge_init_val(const void *blob, int compat_id)
 {
 	int node;
@@ -213,26 +110,6 @@ int socfpga_reset_deassert_bridges_handoff(void)
 				 false, 1000, false);
 }
 
-void socfpga_reset_assert_fpga_connected_peripherals(void)
-{
-	u32 mask0 = 0;
-	u32 mask1 = 0;
-	u32 fpga_pinux_addr = SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
-		if (readl(fpga_pinux_addr)) {
-			mask0 |= per0fpgamasks[i];
-			mask1 |= per1fpgamasks[i];
-		}
-		fpga_pinux_addr += sizeof(u32);
-	}
-
-	setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
-	setbits_le32(&reset_manager_base->per1modrst, mask1);
-	setbits_le32(&reset_manager_base->per0modrst, mask0);
-}
-
 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
 void socfpga_reset_deassert_osc1wd0(void)
 {