imx25: Fix reset

This patch fixes the reset command on imx25. The watchdog registers are 16
bits in size and not 32. This patch also adds the service register codes as
constants.

Signed-off-by: Matthias Weisser <weisserm@arcor.de>

arch/arm/cpu/arm926ejs/mx25/reset.c

@@ -43,14 +43,14 @@ void reset_cpu (ulong ignored)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */
-	writel (0x00000000, &regs->wcr);
+	writew(0, &regs->wcr);
 
 	/* Write Service Sequence */
-	writel (0x00005555, &regs->wsr);
-	writel (0x0000AAAA, &regs->wsr);
+	writew(WSR_UNLOCK1, &regs->wsr);
+	writew(WSR_UNLOCK2, &regs->wsr);
 
 	/* Enable watchdog */
-	writel (WCR_WDE, &regs->wcr);
+	writew(WCR_WDE, &regs->wcr);
 
 	while (1) ;
 }

arch/arm/include/asm/arch-mx25/imx-regs.h

@@ -108,11 +108,11 @@ struct gpt_regs {
 
 /* Watchdog Timer (WDOG) registers */
 struct wdog_regs {
-	u32 wcr;	/* Control */
-	u32 wsr;	/* Service */
-	u32 wrsr;	/* Reset Status */
-	u32 wicr;	/* Interrupt Control */
-	u32 wmcr;	/* Misc Control */
+	u16 wcr;	/* Control */
+	u16 wsr;	/* Service */
+	u16 wrsr;	/* Reset Status */
+	u16 wicr;	/* Interrupt Control */
+	u16 wmcr;	/* Misc Control */
 };
 
 /* IIM control registers */
@@ -308,7 +308,9 @@ struct iim_regs {
 #define GPT_CTRL_TEN		1		/* Timer enable	*/
 
 /* WDOG enable */
-#define WCR_WDE 0x04
+#define WCR_WDE 		0x04
+#define WSR_UNLOCK1		0x5555
+#define WSR_UNLOCK2		0xAAAA
 
 /* FUSE bank offsets */
 #define IIM0_MAC		0x1a