armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by:
York Sun <yorksun@freescale.com>
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- arch/arm/cpu/armv8/fsl-layerscape/cpu.c 107 additions, 14 deletionsarch/arm/cpu/armv8/fsl-layerscape/cpu.c
- arch/arm/include/asm/arch-fsl-layerscape/config.h 6 additions, 0 deletionsarch/arm/include/asm/arch-fsl-layerscape/config.h
- arch/arm/include/asm/arch-fsl-layerscape/cpu.h 9 additions, 5 deletionsarch/arm/include/asm/arch-fsl-layerscape/cpu.h
- board/freescale/ls1043aqds/ddr.c 9 additions, 0 deletionsboard/freescale/ls1043aqds/ddr.c
- board/freescale/ls1043ardb/ddr.c 15 additions, 0 deletionsboard/freescale/ls1043ardb/ddr.c
- board/freescale/ls2080a/ddr.c 15 additions, 0 deletionsboard/freescale/ls2080a/ddr.c
- board/freescale/ls2080aqds/ddr.c 15 additions, 0 deletionsboard/freescale/ls2080aqds/ddr.c
- board/freescale/ls2080ardb/ddr.c 15 additions, 0 deletionsboard/freescale/ls2080ardb/ddr.c
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