Skip to content
Snippets Groups Projects
Commit defd1e71 authored by Eugeniy Paltsev's avatar Eugeniy Paltsev Committed by Alexey Brodkin
Browse files

CLK: HSDK: fix HDMI clock calculation


HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.

Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
parent b8f3ce01
No related branches found
No related tags found
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment