ARM: zynq: slcr: Dont modify the reserved bits
Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by:Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by:
Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by:
Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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