Skip to content
Snippets Groups Projects
Commit f60c6fbb authored by Siva Durga Prasad Paladugu's avatar Siva Durga Prasad Paladugu Committed by Michal Simek
Browse files

ARM: zynq: slcr: Dont modify the reserved bits


Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: default avatarSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: default avatarNathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 3ad87ca1
No related branches found
No related tags found
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment