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Commit fb072a3e authored by Chandan Nath's avatar Chandan Nath Committed by Albert ARIBAUD
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ARM:AM33XX: Fix ddr and timer register offset 


This patch is added to update incorrect ddr and timer
register offset.

Signed-off-by: default avatarChandan Nath <chandan.nath@ti.com>
Signed-off-by: default avatarTom Rini <trini@ti.com>
parent f16da746
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