- Dec 09, 2019
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Suman Anna authored
The commit 1b42ab3e ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP") added the core logic to update the kernel device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx family of SoCs. The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though provide a higher performance and can run at a higher clock frequency of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the correct clock rates on these SoCs. Note that this higher clock rate is not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or AM574x SoCs) that follow the ABZ package. Signed-off-by:
Suman Anna <s-anna@ti.com> Reviewed-by:
Lokesh Vutla <lokeshvutla@ti.com>
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Ben Wolsieffer authored
On NixOS, cross compiled kernels have long suffixes that cause them to exceed the current maximum path length. The PXE/TFTP max path length is used for extlinux.conf support as well, which is where this problem usually manifest's itself. Signed-off-by:
Ben Wolsieffer <benwolsieffer@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Vignesh Raghavendra authored
Enable configs related to DMA and Ethernet so as to support networking at U-Boot prompt Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Acked-by:
Grygorii Strashko <grygorii.strashko@ti.com>
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Vignesh Raghavendra authored
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking up on J721e EVM. Signed-off-by:
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Vignesh Raghavendra authored
Add new compatible to handle J721e SoC Signed-off-by:
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Vignesh Raghavendra authored
Get flow ID information for RX DMA channel using dma_get_cfg() interface instead of reading from DT. This is required in order to avoid DT update whenever there is change in the range of flow ID allocated to the host. Signed-off-by:
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Vignesh Raghavendra authored
Implement dma_get_cfg() interface to pass flow id information for DMA clients to use. This is needed because on K3 SoCs, CPSW (ethernet) and UDMA (DMA provider) support "flows" within a given RX DMA channel. This allows different network packets to be segregated while using same RX DMA channel. In order for basic ethernet to work, CPSW slave must be aware of the flow ID allocated for the RX channel by the DMA driver. This interface allows CPSW to query flow ID from DMA provider and configure it in CPSW HW. Signed-off-by:
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Vignesh Raghavendra authored
Sometimes, there would be a need to exchange data between DMA provider and DMA client which are very specific to DMA driver of the SoC/platform and are not generic enough to be put into struct dma. Therefore, introduce dma_get_cfg() interface to get DMA provider specific data from client device. Clients can use unique configuration ID flags to get different configuration data from DMA driver. Signed-off-by:
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Cédric Le Goater authored
Fixes: e7668497 ("net: ftgmac100: convert the RX/TX descriptor arrays") Signed-off-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Joel Stanley <joel@jms.id.au> Acked-by:
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Alex Marginean authored
This bus is used to access internal SoC PHYs. These PHYs are configured by the ENETC driver directly, but it's useful to have command line access to this MDIO to debug the system especially when using new external PHYs. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
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Alex Marginean authored
On some boards MDIO may get stuck if it detects echo on the line. This is a know hardware issue, there is a board fix for it. In case we're running on a board that doesn't have the fix, we don't want to loop here forever and freeze U-Boot. Signed-off-by:
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Alex Marginean authored
This reduces the time needed to establish a link as we don't reset the link each time the interface is used. Our Link capabilities do not change at run-time so there is no need to re-apply PHY configuration each time. Signed-off-by:
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Alex Marginean authored
The original code enabled link speeds up to 1Gbps, but the interface can go up to 2.5G, enable that speed to in PHY AN mask. Signed-off-by:
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Alex Marginean authored
Uses the new dm_eth_phy_connect helper to connect to the PHY to simplify the code. Signed-off-by:
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Alex Marginean authored
The function connects an ethernet device to a PHY using DT information. This API is only available for eth devices with an associated device tree node. Signed-off-by:
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Alex Marginean authored
Renamed dm_mdio_phy_connect arguments dev to mdiodev and addr to phyaddr for a bit more clarity and consistency with the following patches. Also use NULL instead of 0 on error return path. Signed-off-by:
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Andre Przywara authored
Commit b618b370 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig") accidentally set the default *option* TFTP block size to 512 bytes, even though the comment in the code says that this is a terrible choice. Most boards didn't define the symbol before, so they got the default block size of 1468 bytes before, but now use 512 bytes, which is also the fallback. This leads to both abysmal performance and a lot of hashes printed on the screen (one character for every 5K), which is both annoying and slow over serial links. Set the default block size in Kconfig back to the value it had before. This improves TFTP performance from 2.8 MB/s to 6.9 MB/s on a Pine64. Fixes: b618b370 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig") Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Acked-by:
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Alex Marginean authored
Apply 10G PCS init for USXGMII, XFI interface types. Signed-off-by:
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Alex Marginean authored
A couple of optional properties have been introduced for Aquantia PHY allowing the driver to set up wiring related configuration points that are otherwise driven by firmware. Signed-off-by:
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Alex Marginean authored
It defines that PHY nodes must be children on MDIO bus nodes and defines the only required property in U-Boot, reg. This property along with the example provided are copied over from Linux. Signed-off-by:
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Alex Marginean authored
In some cases the link on the system interface of the aquantia PHY comes up after the link on line interface. The link state loop only checks the line side, which may result in first packet sent being lost. Use aquantia_link_is_up instead, which checks both system and line side on gen 2/3 PHYs to avoid losing the 1st packet. Signed-off-by:
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Alex Marginean authored
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses on this interface are normally set up by PHY firmware, but depending on the board they may end up not being unique. Add an optional DT property used to change SMBus address if needed. Signed-off-by:
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Alex Marginean authored
MDI pins up to the RJ45 connector may be reversed on the board and the default PHY configuration applied by firmware may or may not match that. Add an optional DT property to configure MDI reversal for this case. Signed-off-by:
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Alex Marginean authored
If PHY is not ready for data by the time _config is called, reconfigure the PHY system interface to use the proper protocol based on phydev->interface, just in case the defaults set by PHY firmware don't match current configuration. Signed-off-by:
Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by:
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Alex Marginean authored
Uses the data field in phy_driver structure to identify the PHY generation. This is useful for custom configuration as non-generic PHY registers are not 100% compatible between generations. Signed-off-by:
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Alex Marginean authored
The PHY supports XFI and USXGMII, the notable difference being that USX AN is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and detects whether USX AN should be enabled or not using a PHY status register. Keep that functionality too, so we don't break existing drivers. Signed-off-by:
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Signed-off-by:
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Alex Marginean authored
This is useful to carry custom information between the driver structure associated with a specific HW and the driver code. Signed-off-by:
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Alex Marginean authored
Drivers currently use XGMII for XFI and USXGMII and, where needed, use other information to identify the actual protocol on the board. With these two defined drivers can now rely on DT phy-mode property. Signed-off-by:
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Anatolij Gustschin authored
Fix vendor name in MV88E61xx option description. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Reviewed-by:
Chris Packham <judge.packham@gmail.com> Tested-by:
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Anatolij Gustschin authored
Support probing and init for 88E6071 switch. Signed-off-by:
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Anatolij Gustschin authored
On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by:
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Anatolij Gustschin authored
On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by:
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Anatolij Gustschin authored
Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by:
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Nicolas Ferre authored
The KSZ8081 PHY has a factory test mode which is set at the de-assertion of the reset line based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a pull-up, the factory test mode should be cleared by manually writing a 0 (according to the datasheet). Create another ksz8081_config function to handle this case. Suggested-by:
Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by:
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Michael Walle authored
device_probe() may fail in which case the seq_id will be -1. Don't display these devices during startup. While this is only a cosmetic change, the return value of eth_initialize() will also change to the actual number of available devices. The return value is only used in spl_net to decide whether there are any devices to boot from. So returning only available devices is also more correct in that case. Signed-off-by:
Michael Walle <michael@walle.cc> Acked-by:
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Florin Chiculita authored
Aquantia quad-phys may take longer to initialize. This commit adds a polling mechanism for a global alarm bit that tells if phy init sequence is completed. Signed-off-by:
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Josef Holzmayr authored
This allows passing arbitrary addresses through macb_miiphy_read and macb_miiphy_write, therefore enabling the mii command to access all mdio bus devices instead of only the defined phy. Signed-off-by:
Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> Acked-by:
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Josef Holzmayr authored
To support accessing arbitrary addresses the mii/mdio bus it is necessary that the macb_mdio_read and macb_mdio_write functions do not implicitly use the address of the connected phy. The function signature is extended according to the Linux kernel equivalent. Signed-off-by:
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Stefan Roese authored
I've noticed that in most cases when genphy_update_link() is called, the ethernet driver (mt7628-eth in this case) fails with the first ethernet packets. Resulting in a timeout of the first tftp command. Increasing the delay in the link check look from 1 to 50 ms and moving it below the BMSR register read fixes this issue, resulting in a stable ethernet traffic, even after initial link autonogotiation. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Weijie Gao <weijie.gao@mediatek.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by:
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