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  1. Jan 16, 2012
  3. Jan 13, 2012
  5. Jan 11, 2012
    • Paul Gortmaker's avatar
      sbc8548: Fix up local bus init to be frequency aware · e2b363ff
      Paul Gortmaker authored 
      
The code here was copied from the mpc8548cds support, and it
wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
unconditionally setting the LCRR_EADC bit.  Snooping with a
hardware debugger also showed we had LCRR_DBYP set, since we were
setting it based on a read of an uninitialized lcrr read via
clkdiv.  Borrow from the code in the tqm85xx.c support to add
LBC frequency aware masking of these bits.

This change will correct reliability issues associated with trying
to use the 128MB of LBC 100MHz SDRAM on this board.  Thanks to
Keith Savage for assistance in diagnosing the root cause of this.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      e2b363ff
    • Paul Gortmaker's avatar
      sbc8548: enable support for hardware SPD errata workaround · 3e3262bd
      Paul Gortmaker authored 
      
Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.

After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53.  So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.

Since the old dependency issue of "SPD implies no LBC SDRAM"
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      3e3262bd
    • Paul Gortmaker's avatar
      sbc8548: relocate fixed ddr init code to ddr.c file · 2a6b3b74
      Paul Gortmaker authored 
      
Nothing to see here, just a relocation of the fixed ddr init
sequence to live in the actual ddr.c file itself.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      2a6b3b74
    • Paul Gortmaker's avatar
      sbc8548: Make enabling SPD RAM configuration work · 7e44f2b7
      Paul Gortmaker authored 
      
Previously, SPD configuration of RAM was non functional on
this board.  Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.

We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled.  We can revisit this dependency as the
hardware workaround becomes available.

Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.

This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.

The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs.  But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      7e44f2b7
    • Paul Gortmaker's avatar
      sbc8548: Fix LBC SDRAM initialization settings · 5f4c6f0d
      Paul Gortmaker authored 
      
These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size).  Set the values
by comparing to the register file for the board used during
JTAG init sequence:

	LSDMR1		0x2863B727	/* PCHALL */
	LSDMR2		0x0863B727	/* NORMAL */
	LSDMR3		0x1863B727	/* MRW    */
	LSDMR4		0x4063B727	/* RFEN   */

This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.

The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_0000 _and_ to 0xf400_0000.

We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      5f4c6f0d
    • Paul Gortmaker's avatar
      sbc8548: enable ability to boot from alternate flash · f0aec4ea
      Paul Gortmaker authored 
      
This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module.  Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6.  This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.

To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.

We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.

The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      f0aec4ea