Running on mpc837x without CONFIG_FSL_ESDHC leads to
 i2c1_clk not being set at all. It is bound to clock
 of encryption module. fix this.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

Commit 359ec493 broke support for the
Freescale DMA engine on the 83xx parts. This is due to using registers
which do not exist on 83xx. Remove the attribute register accesses from
the 83xx build.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Cc: York Sun <yorksun@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

This patch add support for the Network Space v2 board and parents, based
on the Marvell Kirkwood 6281 SoC. This include Network Space (Max) v2
and Internet Space v2.

Additional information is available at:
http://lacie-nas.org/doku.php?id=network_space_v2



Signed-off-by: Simon Guinot <sguinot@lacie.com>

This adds support for the keymile Kirkwood BEC portl2 board. This board
relies on the km_arm (km_kirkwood) BEC.

The egiga driver is configured for a 100M full-duplex, A/N off connnection
to the backplane. This board has always ethernet present, because it is
connected to the marvell switch similar to mgcoge3un. The reset_phy
functionality is also the same to mgcoge3un.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

suen3 and suen8 were in first HW version quite different, but
now they are from a u-boot point of view similar. So these
two boards can use the same header file. Other keymile boards
differ only in the usage of the PCI interface. Therefore
a target km_kirkwood_pci was introduced. All targets use
the same header file.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

The phy is also configured with "RGMII clock transitions when data
stable" and "Class A driver for the direct backplane connection".

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

This is defined for all km_kirkwood boards and was not used up to now.
This value was the same for all boards but it could be changed for some
boards (and thus needs to be defined for every board).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

CONFIG_ENV_SIZE for NAND was later in this file overwritten
because we have the environment in i2c eeprom, so remove
this define.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

commit 010a958b
(arm/km: remove CONFIG_SYS_KWD_CONFIG from keymile-common.h)
breaks building keymile arm targets, when u-boot.kwb tries to
generate the binary with mkimage. A simple make <board> or MAKEALL
succeeded because it don't try to build the kirwood binary at the end.

Due this commit we use the CONFIG_SYS_KWD_CONFIG from the
arch-kirkwood/config.h and it was removed from the board config.
But it was forgotten to include the header. Now the header is included
in km_arm.h. Some other defines were obsolete due to this include,
these are also removed in this commit.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

Some boards e.g. keymile arm boards have CONFIG_CMD_I2C switched on
but they use soft i2c on kirkwood. So don't switch CONFIG_I2C_MVTWSI
on in this case.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

* Fix compiler error for cpu at91sam9, if lowlevel init is enabled
* use correct ATMEL_ name scheme to define ATMEL_BASE_SDRAMC

Signed-off-by: Jens Scharsig

This patch removes the board implemenatation for flash driver which can now
safely switched to the common cfi driver.

Compile tested for all atstk100x boards, runtime tested on atstk1002.

Signed-off-by: Andreas Bießmann <biessmann@corscience.de>

The at91rm9200_usart driver could be fully replaced by atmel_usart driver.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Eric Bénard <eric@eukrea.com>

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Jens Scharsig <js_at_ng@scharsoft.de>
Acked-by: Jens <Scharsig&lt;js_at_ng@scharsoft.de>
Tested-by: Jens Scharsig<js_at_ng@scharsoft.de> (for eb_cpux9k2 board)

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

This is a copy of arm926ejs/at91 api for perpherial initialisation.
At the moment we just need the usart part of the api.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

This patch enables the new clock features from arm920t/at91/clock.c. This
is an required step to get at91rm9200_usart replaced by atmel_usart driver.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Jens Scharsig <js_at_ng@scharsoft.de>
Cc: Eric Bénard <eric@eukrea.com>

This patch adds an copy of arm926ejs/at91/clock.c to arm920t/at91. The
arm926ejs specialities are removed from arm920t version and vice versa.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

This patch sets the ATMEL_PMX_AA_TXD2 to the correct value.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Jens Scharsig <js_at_ng@scharsoft.de>
CC: eric@eukrea.com
Acked-by: Eric Bénard <eric@eukrea.com>

commit 0015de1a (MX5: Make the weim structure complete) fixed the name for
the WEIM registers in order to match with the MX51/MX53 manuals.

Fix the WEIM register for vision2 board so that it can build again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Enable dcache and arch memset/memcpy for speed reasons
Remove of config.mk and some environment overwrites
Some generic cleanup

Signed-off-by: Matthias Weisser <weisserm@arcor.de>

Define CONFIG_SYS_SDRAM_BASE to physical SDRAM address
and CONFIG_SYS_INIT_SP_ADDR to physical SRAM address

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Kyungmin Park <kyungmin.park@samsung.com>

As implemented now the timer used to implement __udelay counts
to 0xffffffff and then gets stuck there because the the programmed
reload value is 0xffffffff.  This value is not only wrong but
illegal according to the reference manual.

One can reproduce the bug by leaving a board at the u-boot prompt
for sometime then issuing a sleep command.  The sleep will hang
forever.

The timer is a count up timer that reloads as it rolls over
from 0xffffffff so the correct load value is 0.

Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce
a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff.

Signed-off-by: John Rigby <john.rigby@linaro.org>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>

Signed-off-by: Tom Warren <twarren@nvidia.com>

Signed-off-by: Tom Warren <twarren@nvidia.com>

Signed-off-by: David Müller <d.mueller@elsoft.ch>

Signed-off-by: David Müller <d.mueller@elsoft.ch>

Signed-off-by: David Müller <d.mueller@elsoft.ch>

adapt s5pc1xx to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>

adapt omap3 to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>

adapt omap4 to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>

PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430

Add support for some of the key PL310 operations
	- Invalidate all
	- Invalidate range
	- Flush(clean & invalidate) all
	- Flush range

Signed-off-by: Aneesh V <aneesh@ti.com>

1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
   than a range flush on the entire memory(flush_cache())

   Provide a default implementation for flush_dcache_all()
   for backward compatibility and to avoid build issues.

Signed-off-by: Aneesh V <aneesh@ti.com>

- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
	- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
	- Make changes according to the new framework

Signed-off-by: Aneesh V <aneesh@ti.com>

Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:

CONFIG_L2_OFF	     -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF

Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
 * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
 * Changed all three flags to the final names suggested as above
   and accordingly changed the commit message