The board maintainer states:

    The GTH board is obsolete and has not been manufactured for
    several years.
    To my knowledge, no recent U-Boot build has been tested on that
    card.

So drop support for this board.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Thomas Lange <thomas@corelatus.se>
Acked-by: Thomas <Lange&lt;thomas@corelatus.se>

Signed-off-by: Anatolij Gustschin <agust@denx.de>

The code to map SERDES configs to slot names is board specific and not
chip specific.  Thus it should live in board/freescale/p1022ds/ and not
in arch/powerpc/cpu/.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Add 'errata' command to report what errata we workaround.  Report
workaround for erratum SATA-A001 on P1022/P1013.

Also sorted the CONFIG_CMD_* list.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Specifics:

1) 36-bit only
2) Booting from NOR flash only
3) Environment stored in NOR flash only
4) No SPI support
5) No DIU support

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Enables the Intel Pro/1000 PT Gb Ethernet PCI-E Network Adapter
configuration support for P1/P2 RDB.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that
we can capture the LAW target for a given PCI or PCIE controller.  Also update
the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the
LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure.

This will allow future PCI[E] code to configure the LAW target automatically,
rather than requiring each board to it for each PCI controller separately.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The e5500 has a link register stack and segment target address cache.
Its safe to enable these bits on older e500 cores as the bits are
implemented in the register.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Each platform had its own version of the upmconfig, despite the
init process being identical.  Now that we have a spot for common
lbc code, create a common upmconfig() there.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The new command dumps the TLBCAM, the LAWs, and the BR/OR regs.
Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Add printing of LAWBARH/LAWBARL for FSL_CORENET platforms.

Signed-off-by: Becky Bruce <Beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The current code redefines functions based on FSL_CORENET_ vs not -
create macros/inlines instead that hide the differences.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

This dumps out the contents of TLB1 on 85xx-based systems.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code.  Create a TSIZE_TO_BYTES macro to deal with the conversion
from the MAS field to an actual size instead of duplicating this in code.
There are a few misc other minor cleanups.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers.  Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Some parts that have an Enhanced Local Bus Controller weren't
setting CONFIG_FSL_ELBC.  Fix this so we can use this define
properly going forward (currently it's only used if PHYS_64BIT is
set, which meant not all platforms needed to have it set correctly).

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

We have several boards that use the same ICS307 CLK chip to drive the
System clock and DDR clock.  Move the code into a common location so we
share it.

Convert the P2020DS board as the first to use the new common ICS307
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Timur Tabi <timur@freescale.com>

The various boards that have PIXIS FPGAs have slightly different
register definitions, however there is some common functionality (like
reset, ICS307 clk control, etc) that can be shared.

The struct definition exists for MPC8536DS, MPC8544DS, MPC8572DS,
MPC8610HPCD, and MPC8641HPCN boards.

Also fixed ngpixis to be __packed__ instead of aligned.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

If we explicitly disabled a core remove it from the dtb we pass on to
the kernel.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

We may have cpu-handles pointing to the cpu nodes we delete.  If so we
should delete the handles as well.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x.
Parts with newer SEC h/w versions will increment the number to
accomodate incompatible code changes.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

This patch adds support for Aeronix Zipit Z2 handheld.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

This patch adds support for the Voipac PXA270 board. The support includes:
- Ethernet
- USB
- MMC
- NOR Booting
- OneNAND Booting
- LCD
- HDD

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

This patch adds macros for the following purposes:
- GPIO configuration
- SDRAM configuration
- Wakeup
- Clock configuration
- Interrupt controller configuration
These macros are intended to replace numerous copies of the same code.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>