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  1. Jul 04, 2011
    • Aneesh V's avatar
      armv7: adapt omap3 to the new cache maintenance framework · 45bf0585
      Aneesh V authored 
      
adapt omap3 to the new layered cache maintenance framework

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
      45bf0585
    • Aneesh V's avatar
      armv7: adapt omap4 to the new cache maintenance framework · 8b457fa8
      Aneesh V authored 
      
adapt omap4 to the new layered cache maintenance framework

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
      8b457fa8
    • Aneesh V's avatar
      armv7: add PL310 support to u-boot · 93bc2193
      Aneesh V authored 
      
PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430

Add support for some of the key PL310 operations
	- Invalidate all
	- Invalidate range
	- Flush(clean & invalidate) all
	- Flush range

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
      93bc2193
    • Aneesh V's avatar
      arm: minor fixes for cache and mmu handling · e05f0079
      Aneesh V authored 
      
1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
   than a range flush on the entire memory(flush_cache())

   Provide a default implementation for flush_dcache_all()
   for backward compatibility and to avoid build issues.

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
      e05f0079
    • Aneesh V's avatar
      armv7: integrate cache maintenance support · c2dd0d45
      Aneesh V authored 
      
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
	- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
	- Make changes according to the new framework

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
      c2dd0d45
    • Aneesh V's avatar
      armv7: rename cache related CONFIG flags · e47f2db5
      Aneesh V authored 
      
Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:

CONFIG_L2_OFF	     -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
V2:
 * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
 * Changed all three flags to the final names suggested as above
   and accordingly changed the commit message
      e47f2db5
    • Aneesh V's avatar
      armv7: cache maintenance operations for armv7 · 2c451f78
      Aneesh V authored 
      
- Add a framework for layered cache maintenance
	- separate out SOC specific outer cache maintenance from
	  maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
  caches known to ARMv7 CPUs. For instance in Cortex-A8 these
  opertions will affect both L1 and L2 caches. In Cortex-A9
  these will affect only L1 cache

- D-cache operations supported:
	- Invalidate entire D-cache
	- Invalidate D-cache range
	- Flush(clean & invalidate) entire D-cache
	- Flush D-cache range
- I-cache operations supported:
	- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
  used

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
      2c451f78
    • Aneesh V's avatar
      arm: make default implementation of cache_flush() weakly linked · 4c93da7c
      Aneesh V authored 
      
make default implementation of cache_flush() weakly linked so that
sub-architectures can override it

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
      4c93da7c
  3. Jul 01, 2011
  5. Jun 30, 2011
  7. Jun 29, 2011
    • Mike Frysinger's avatar
      cfi_flash: reverse geometry for newer STM parts · 4c2105cb
      Mike Frysinger authored 
      
For newer STM parts where CFI >= 1.1, there is a byte in the extended
structure that declares the flash layout type (just like the AMD parts),
so key off of that to find out when we need to reverse the geometry.

This can be seen with M29W640 parts where U-Boot does:
Bank # 1: CFI conformant FLASH (16 x 16)  Size: 8 MB in 135 Sectors
  AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED
  Erase timeout: 8192 ms, write timeout: 1 ms
  Buffer write timeout: 1 ms, buffer size: 16 bytes

  Sector Start Addresses:
  20000000   RO   20002000   RO   20004000   RO   20006000   RO   20008000   RO
  2000A000   RO   2000C000   RO   2000E000   RO   20010000   RO   20020000   RO
  ...

But Linux does:
physmap platform flash device: 00800000 at 20000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank.
                 Manufacturer ID 0x000020 Chip ID 0x0022ed
physmap-flash.0: Swapping erase regions for top-boot CFI table.

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
Signed-off-by: default avatarStefan Roese <sr@denx.de>
      4c2105cb
  9. Jun 27, 2011
  11. Jun 25, 2011
  13. Jun 23, 2011