Signed-off-by: gururaja hebbar <gururajakr@sanyo.co.in>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Current libata.h of u-boot is out of sync from linux kernel,
this patch make it be consistent with linux kernel.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Tor Krill <tor@excito.com>

It should access with 16-bit instead of 8-bit

Now it uses the generic memcpy with 8-bit access. It means it reads wrong data from OneNAND.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Remove test for CONFIG_MPC5200 in drivers/pci/pci_auto.c and define
CONFIG_PCIAUTO_SKIP_HOST_BRIDGE in related board configuration files.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: Dave Liu <daveliu@freescale.com>

Signed-off-by: Dave Liu <daveliu@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

This patch adds an i2c driver for Freescale i.MX processors

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

When the LM73 temperature sensor measures a temperature below 0 C, the
current driver does not perform sign extension, so the result returned is
512 C too high.  This patch fixes the problem, and does general cleanup
of the code.

Signed-off-by: Larry Johnson <lrj@acm.org>

Some NOR flash chip from Spansion, for example, the s29ws-n MirrorBit
series require different addresses for buffered write commands. Define a
configuration option to support buffered writes on those chips. A more
elegant solution would be to automatically detect those chips by parsing
their CFI records, but that would require introduction of a fixup table
into the cfi_flash driver.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

Reverting became necessary after it turned out that the patches in
the u-boot-arm repo were modified, and in some cases corrupted.

This reverts the following commits:

	066bebd6
	7a837b73
	c88ae205
	a147e56f
	d6674e0e
	8c8463cc
	c98b47ad
	8bf69d81
	8c16cb0d
	a574a738
	1377b558
	1704dc20

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Michal Simek <monstr@monstr.eu>

Signed-off-by: Michal Simek <monstr@monstr.eu>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.

Signed-off-by: Tor Krill <tor@excito.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

This patch makes SPARC/LEON processors able to read and write
to the SMC91111 chip using the chip external I/O bus of the memory
controller. This patchs defines the standard in and out macros
expected by the SMC9111 driver.

To access that I/O bus one must set up the memory controller
(MCTRL or FTMCTRL) correctly. It is assumed that the user sets
up this correctly when the other MCTRL parameters are set up. It
can be set up from the board configuration header file.

Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

Support for booting from internal DataFlash, external DataFlash card
or NAND flash is available.

Signed-off-by: Stelian Pop <stelian@popies.net>

DataFlash partition information has become a mess. This patch
defines a single partition scheme for Atmel DataFlashes. This partition
scheme will be used by all AT91CAP9 and AT91SAM9 boards.

Signed-off-by: Stelian Pop <stelian@popies.net>

This patch adds a driver for the following smsc network controllers:
LAN9115
LAN9116
LAN9117
LAN9215
LAN9216
LAN9217

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

This patch adds an i2c driver for Freescale i.MX processors

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

Add 82541ER device with latest integrated IGP2 PHY.
Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

GRETH is an Ethernet 10/100 or 10/100/1000 MAC with out without
a debug link (EDCL). The GRETH core is documented in GRIP.pdf
available at www.gaisler.com.

If the GRETH has GigaBit support (GBIT, Scatter gather, checksum
offloading etc.) can be determined by a bit in the control register.
The GBIT MAC is supported by operating in GRTEH 10/100 legacy mode.

Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address.
SPARC CPUs implement flash_read64 which calls __raw_readq.

For current SPARC architectures (LEON2 and LEON3) each read from the
FLASH must lead to a cache miss. This is because FLASH can not be set
non-cacheable since program code resides there, and alternatively disabling
cache is poor from performance view, or doing a cache flush between each
read is even poorer.

Forcing a cache miss on a SPARC is done by a special instruction "lda" -
load alternative space, the alternative space number (ASI) is processor
implementation spcific and can be found by including <asm/processor.h>.

Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>

Add entry for 512Kx16 AMD flash to jedec_table.
Read out 16bit device id if chipwidth is 16bit.
Fixed coding style after Stefans feedback

Signed-off-by: Tor Krill <tor@excito.com>

Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Receive FIFO level register is different in SH4A.
Because register is different, cannot occasionally receive data.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

SH7780 is CPU of Renesas Technology.
This CPU has
 - CPU clock 400MHz
 - PCI support
 - DDR-SDRAM controller
 - etc ...

Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add support to the Freescale I2C driver (fsl_i2c.c) for setting and querying
the I2C bus speed.  Current 8[356]xx boards define the CFG_I2C_SPEED macro,
but fsl_i2c.c ignores it and uses conservative value when programming the
I2C bus speed.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Add the Freescale on-chip SATA controller driver to u-boot,
The SATA controller is used on the 837x and 8315 targets,
The driver can be used to load kernel, fs and dtb.

The features list:
- 1.5/3 Gbps link speed
- LBA48, LBA28 support
- DMA and FPDMA support
- Two ports support

Signed-off-by: Dave Liu <daveliu@freescale.com>

add simple libata support in u-boot

Signed-off-by: Dave Liu <daveliu@freescale.com>

original ata_piix driver is using IDE framework, not real
SATA framework. For now, the ata_piix driver is only used
by x86 sc520_cdp board. This patch makes the ata_piix driver
use the new SATA framework, so

- remove the duplicated command stuff
- remove the CONFIG_CMD_IDE define in the sc520_cdp.h
- add the CONFIG_CMD_SATA define to sc520_cdp.h

Signed-off-by: Dave Liu <daveliu@freescale.com>