- increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
- use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
- remove "Unlock Bypass" mode, because macronix flashes do not support
  this mode officially
- fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
  for Intel compatible flashes, not for AMD compatible.
Patch by Martin Krause, 15 Feb 2006

(for erase errors and timeout errors)
Patch by Martin Krause, 14 Feb 2006

The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006

Some code cleanup

Patch by Martin Krause, 20 Mar 2006

Signed-off-by: Martin Krause <martin.krause@tqs.de>

All MII configuration is done via FEC1 registers. But MII_SPEED was
configured according to FEC used. So if only FEC2 was used, this caused
the real MII_SPEED register in FEC1 to stay uninitalised, what lead
to "mii_send STUCK!" messages. Fix: always configure MII_SPEED on FEC1
only.

Patch by Markus Klotzbuecher, 12 Jul 2006

Notes:
- Board-dependend code for RPXLITE and RPXCLASSIC-based boards
  placed to the drivers/rpx_pmcia.c file to avoid duplication.
  Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
- drivers/i82365.c has been split into two parts located at
  board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
  the only boards using CONFIG_82365).
- Changes were tested for clean build and *very* *few* boards.

Set Timer Clock Select to use CPU clock as a timer input source.

Enabled it for Yucca board.

  Patch from Richard Danter, 12 Aug 2005

Patch by Thomas Lange, Aug 11 2005

Patch by Martin Krause, 8 Jun 2006

This patch supports two serial consoles on boards with
a MPC5xxx CPU. The console can be switched at runtime
by setting stdin, stdout and stderr to the desired serial
interface (serial0 or serial1). The PSCs to be used as
console port are definded by CONFIG_PSC_CONSOLE
and CONFIG_PSC_CONSOLE2.
See README.serial_multi for details.

If the bus is blocked because of a previously interrupted
transfer, up to eleven clocks are generated on the I2CSCL
line to complete the transfer and to free the bus.
With this fix pin I2CSCL (PG6) is really configured as GPIO
so the clock pulses are really generated.
Patch by Martin Krause, 04 Apr 2006

Patch by Thomas Waehner, 07 Mar 2006