- Jun 06, 2007
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Rodolfo Giometti authored
Using some (very) slow USB keys cause the USB host controller buffers are not ready to be read by the CPU so we need an extra delay before reading the USB storage data. Signed-off-by:
Rodolfo Giometti <giometti@linux.it>
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Markus Klotzbuecher authored
Thanks to Liew Tsi Chung <Tsi-chung.Liew@freescale.com> for pointing this out. Signed-off-by:
Markus Klotzbuecher <mk@denx.de>
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- May 29, 2007
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- May 27, 2007
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Wolfgang Denk authored
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Bartlomiej Sieka authored
Signed-off-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
Enable redundant environment, add a MTD partition for it; also add env. variable command for passing MTD partitions to the kernel command line. Signed-off-by:
Piotr Kruszynski <ppk@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
Allow passing longer command line to the kernel - useful especially for passing MTD partition layout. Signed-off-by:
Piotr Kruszynski <ppk@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
Signed-off-by:
Piotr Kruszynski <ppk@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A have a page write capability of two bytes", and "This device offers fast (1ms) byte write". Add 3ms of extra delay. Signed-off-by:
Piotr Kruszynski <ppk@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which networking does not function. This commit switches PHY to TX mode by clearing the FX_SEL bit of Mode Control Register. It also reverses commit 008861a2, i.e., a temporary workaround. Signed-off-by:
Grzegorz Bernacki <gjb@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
Signed-off-by:
Piotr Kruszynski <ppk@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
Signed-off-by:
Jan Wrobel <wrr@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by:
Grzegorz Bernacki <gjb@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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Bartlomiej Sieka authored
Signed-off-by:
Jan Wrobel <wrr@semihalf.com> Signed-off-by:
Marian Balakowicz <m8@semihalf.com> Acked-by:
Bartlomiej Sieka <tur@semihalf.com>
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- May 24, 2007
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Stefan Roese authored
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Stefan Roese authored
As pointed out by Bruce Adler <bruce.adler@acm.org> this patch fixes a small bug in the 405EZ OCM initialization. Thanks for spotting. Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
This patch updates the Acadia (405EZ) support for the new 1.1 board revision. It also adds support for NAND FLASH via the 4xx NDFC. Please note that the jumper J7 must be in position 2-3 for this NAND support. Position 1-2 is for NAND booting only. NAND booting support will follow later. Signed-off-by:
Stefan Roese <sr@denx.de>
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- May 22, 2007
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Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
This patch adds support for 405 PPC's to the 4xx NAND driver ndfc.c. This is in preparation for the new AMCC 405EZ. Signed-off-by:
Stefan Roese <sr@denx.de>
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- May 21, 2007
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Stefan Roese authored
As spotted by Bruce Adler this patch fixes an initialization problem for the 405EZ OCM. Signed-off-by:
Stefan Roese <sr@denx.de>
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- May 18, 2007
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- May 16, 2007
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Stefano Babic authored
Signed-off-by:
Stefano Babic <sbabic@denx.de>
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Jeffrey Mann authored
Because the Sequoia board does not boot with an EBC faster than 66MHz, the clock divider are changed after the initial boot process. This allows for maximum clocking speeds to be achieved on newer boards. Sequoia boards with 666.66 MHz processors require that the EBC divider be set to 3 in order to start the initial boot process at a slower EBC speed. After the initial boot process, the divider can be set back to 2, which will cause the boards to run at 83.333MHz. This is backward compatible with boards with 533.33 MHz processors, as these boards will already be set with an EBC divider of 2. Signed-off-by:
Jeffrey Mann <mannj@embeddedplanet.com>
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- May 15, 2007
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Wolfgang Denk authored
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Wolfgang Denk authored
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Wolfgang Denk authored
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- May 14, 2007
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Wolfgang Denk authored
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Wolfgang Denk authored
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- May 11, 2007
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Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de>
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- May 10, 2007
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Piotr Kruszynski authored
definition.
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- May 08, 2007
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Michal Simek authored
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Michal Simek authored
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Michal Simek authored
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Piotr Kruszynski authored
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Bartlomiej Sieka authored
environment.
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Bartlomiej Sieka authored
eliminates networking problems in Linux (timeouts).
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Bartlomiej Sieka authored
to allow booting of FDT-expecting kernels.
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- May 07, 2007
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git://www.denx.de/git/u-bootMichal Simek authored
Conflicts: include/asm-microblaze/microblaze_intc.h include/linux/stat.h
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