For P1022 SATA host controller, the data snoop bit of DW3 in PRDT
is moved to bit28.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

After power on, the SATA host controller of P1022 Rev1 is configured
in legacy mode instead of the expected enterprise mode.

Software needs to clear bit[28] of HControl register to change to
enterprise mode after bringing the host offline.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

add the macro definition for Rtt_Nom termination value for DDR3

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Added some needed fines and some misc additional defines
used by p4080 initialization.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Extend pin control and clock control to GUTS memory map

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency.  It should be synchronous with the platform
frequency.  CPU frequency is based on platform frequency in synchronous
mode.

Also fix:

* Fixes the bit mask for DDR_SYNC (RCWSR5[184])
* Corrects the detection of synchronous mode.

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

While we had ft_pci_board_setup it wasn't being called by
ft_board_setup.  Fix that so we actually update the device tree PCI
nodes on P1_P2_RDB boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has been introduced to do data transfer using CPU.

Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>

As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>

This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.

Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch adds a callpoint in i2c_init that allows board specific
i2c board initialization (typically for i2c bus reset) that is called
after i2c_init operations, allowing the i2c_board_late_init function
to use the pre-configured i2c bus speed and slave address.

Signed-off-by: Scott McNutt <smcnutt@psyent.com>

Merge cpu and lib cache code.
Flush cache before disabling.

Signed-off-by: Michal Simek <monstr@monstr.eu>

There is used max cache size on system which doesn't define
cache size.

Signed-off-by: Michal Simek <monstr@monstr.eu>

WB cache use different instruction that WT cache but the major code
is that same. That means that wdc.flush on system with WT cache
do the same thing as before.

You need newer toolchain with wdc.flush support.

Signed-off-by: Michal Simek <monstr@monstr.eu>

env_relocation should be called first.
Added stdio_init too.

Signed-off-by: Michal Simek <monstr@monstr.eu>

It is more accurate to show that caches are OFF instead of FAIL.

Signed-off-by: Michal Simek <monstr@monstr.eu>

It is better to read ivr and react on it than do long parsing from
two regs. Interrupt controller returs actual irq number.

Signed-off-by: Michal Simek <monstr@monstr.eu>

Move FSL out of interrupt controller.

Signed-off-by: Michal Simek <monstr@monstr.eu>

I would like to handle case where system doesn't contain
intc that's why I need timer initialization out of intc code.

Signed-off-by: Michal Simek <monstr@monstr.eu>

It is ancient code. There is possible to save several instructions
just if we use offset instead of addik

Signed-off-by: Michal Simek <monstr@monstr.eu>

This patch adds FDT (flattened device tree) support to microblaze arch.

Tested with Linux arch/microblaze kernels with and without compiled in
FDT on Xilinx ML506 board.

Signed-off-by: Arun Bhanu <arun@bhanu.net>
Signed-off-by: Michal Simek <monstr@monstr.eu>

The 440SPe Rev. A is quite old and newer 440SPe boards don't need support
for this CPU revision. Since removing support for this older version
simplifies the creation for newer U-Boot ports, this patch now enables
440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By
defining this in the board config header, Rev. A will still be supported.
Otherwise (default for newer board ports), Rev. A will not be supported.

Signed-off-by: Stefan Roese <sr@denx.de>

The latest changes increased the size of the alpr image a bit more.
Now it doesn't fit into the 256k reserved for it. This patch now removes
the commands "loads" and "loadb" which are not needed in the production
systems.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pieter Voorthuijsen <pieter.voorthuijsen@prodrive.nl>

Also fix up some whitespace issues that were introduced when moving
directory locations.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>