These types should be 64 bits long to reflect the fact that physical
addresses and the size of physical areas of memory are more than 32 bits
long.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

The use of post-increment with a do-while loop results in
the loop going one step too far when handling relocation fixups.

In about 1/100 cases this would cause it to hang.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

U-boot is unable to actually use that memory and it can
cause problems with relocation if it tries to.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

Enable this option to support booting a zImage.

Signed-off-by: Simon Glass <sjg@chromium.org>

This fixes the following warning:

zimage.c:312: Warning: indirect jmp without `*'

Also fixed these warnings to keep checkpatch quiet:

warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline

Signed-off-by: Simon Glass <sjg@chromium.org>

This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

Imported from Linux 3.1 with a few modifications to suit U-Boot

Signed-off-by: Simon Glass <sjg@chromium.org>

This function can be used by boards which want to do some clean-up
before booting a zImage.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

Add functions to enable/disable the data cache.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.

This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

To maintain the initialization state of the timestamp facility, thesq
pointer to the CBMEM section containing the timestamp table should be
kept in the .data section (so that it is maintained across u-boot
relocation).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

This change turns on the code which allows u-boot to add
timestamps to the timestamp table created by coreboot.

Since u-boot does not use the tsc_t like structure to represent
HW counter readings, this structure is being replaced by 64 bit
integer.

The timestamp_init() function is now initializing the base timer
value used by u-boot to calculate the HW counter increments.

Timestamp facility is initialized as soon as the timestamp table
pointer is found in the coreboot table. The u-boot generated
timer events' ID will start at 1000 to clearly separate u-boot
events from coreboot events in the timer trace.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

Put this function in the u-boot-x86.h header file. We could instead create
timer.h perhaps.

We support setting a base time, and reading the time relative to this base.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.

BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
  them all, or even keep track of the new ones.

So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

Coreboot uses this controller to implement GPIO access.

Signed-off-by: Simon Glass <sjg@chromium.org>

Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>

This patch fixes an issue with overlapping PCI regions
on boards with more than 64MB RAM.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>

This new make target "u-boot-img.bin" consists of the U-Boot
SPL image with the real, full-blown U-Boot image directly
attached to it. The full-blown U-Boot image has the mkimage
header included, with its load-address and entry-point.

This will be used by the upcoming a3m071 MPC5200 board port.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch enabled boards using the SPL framework to set
an entry point in the U-Boot mkimage image "u-boot.img".
Until now the entry point in the header has been set to 0.
By setting CONFIG_SYS_UBOOT_START in the board header, boards
can override this default location.

This will be used by the upcoming a3m071 MPC5200 board port.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch adds support for the a3m071 board based on the
MPC5200.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch adds SPL booting support (NOR flash) for the
MPC5200 platforms.

Signed-off-by: Stefan Roese <sr@denx.de>

With this patch, getenv_f() can be included easily into the SPL
binary. With this, SPL boards can now use getenv_f() to read
environment variables (e.g. to detect if the OS or U-Boot shall
be executed).

In the approach this is done for env stored in NOR flash, as this
will be used by an upcoming MPC5200 board port.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch enables the SPL framework to be used on powerpc platforms
and not only ARM.

timer_init() does not exist on PPC systems. The timer (decrementer) is
initialized and enabled in interrupt_init() here. And currently
interrupt_init() is called after relocation to SDRAM. Since the only
powerpc SPL implementation (a3m071) doesn't need a timer, let's remove
this timer_init() call for PPC systems.

Signed-off-by: Stefan Roese <sr@denx.de>

By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch prevents u-boot from "spamming" random progress codes on
a port 80 "post card".
The previous version of this patch just removed the delays in the "slow"
IO functions, as they do not need to be slow, however, this patch is
less intrusive.

It uses another unused port that is often used by BIOSes (and the Linux
Kernel) for small delay timing purposes.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

This option protects the printf() functions from overflow.

Signed-off-by: Simon Glass <sjg@chromium.org>

Fix a small comment typo.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

The i386 version of io.h depends on the phys_addr_t type which is defined in
types.h. It wasn't including that explicitly, and was working presumably
because the other files including it had already included types.h themselves
directly or indirectly. This change fixes that.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

The microsecond timer is not currently implemented, but add a dummy
implementation for now.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

This function provides an opportunity for some last minute cleanup and
reconfiguration before control is handed over to Linux. It's possible this
may need to do something in the future, but for now it's left empty. It's set
up as a weak symbol so it can be overridden if necessary on a case by case
basis.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

The device tree now includes the necessary console configuration
information.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>

This change adds a pointer to the global data structure in x86 to point to
the device tree. This mirrors an identical pointer in ARM.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

Add a basic driver for the coreboot framebuffer.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

This file is no longer needed for coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>

We don't want this for coreboot, so provide a way of compiling it out.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

We want to support VGA, serial, USB keyboard and the Coreboot memory
console buffer.

Signed-off-by: Simon Glass <sjg@chromium.org>

This command is useful to allow to observe messages generated by
coreboot and u-boot until present. In particular it is handy when
u-boot is instrumented to fall through into console mode on startup
errors.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

This patch builds upon the recently introduced CBMEM console
feature of coreboot.

CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.

Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.

>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:

vvvvvvvvvvvvvvvvv
SCSI:  AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure  quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^

Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>