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  1. Feb 12, 2019
  2. Feb 11, 2019
    • Tom Rini's avatar
      Merge branch 'master' of git://git.denx.de/u-boot-i2c · f94fa0e9
      Tom Rini authored
      - DM I2C improvements
      f94fa0e9
    • Tom Rini's avatar
      Merge git://git.denx.de/u-boot-marvell · f4992977
      Tom Rini authored
      - Fix BUILD_TARGET for ARCH_MVEBU from Baruch
      - Fix MVEBU PCIe reset issues from Baruch
      - Increase DDR stability on x530 from Chris
      f4992977
    • Chris Packham's avatar
      ARM: mvebu: x530: use MV_DDR_FREQ_SAR · a6ac775b
      Chris Packham authored
      
      MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware
      strapping. This also has the side effect of running the DDR clock in
      synchronous mode with the CPU core clock rather than from an independent
      PLL. We've seen this improve reliability in operation across a number of
      boards and temperature ranges.
      
      Signed-off-by: default avatarChris Packham <judge.packham@gmail.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      a6ac775b
    • Baruch Siach's avatar
      Kconfig: fix BUILD_TARGET for ARCH_MVEBU · 0ef69208
      Baruch Siach authored
      
      Commit dc146ca1 ("Kconfig: Migrate CONFIG_BUILD_TARGET") made the
      mvebu default build target depend on CONFIG_SPL_BUILD. Unfortunately,
      there is no such Kconfig symbol. Use the CONFIG_SPL symbol instead to
      fix that.
      
      Cc: Jagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      Reviewed-by: default avatarJagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      0ef69208
    • Baruch Siach's avatar
      arm: mvebu: cf gt-8k: dts: add PCIe slot reset support · d7f165cf
      Baruch Siach authored
      
      Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices
      on Clearfog GT-8K.
      
      Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      d7f165cf
    • Baruch Siach's avatar
      pcie: designware: mvebu: fix reset release polarity · 6664a0e5
      Baruch Siach authored
      
      The dm_gpio_set_value() routine sets signal logical level, with
      GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
      (asserted), while reset inactive value is 0 (de-asserted). Fix the reset
      toggle code to set the correct reset logic value.
      
      Reported-by: default avatarSven Auhagen <sven.auhagen@voleatech.de>
      Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      6664a0e5
    • Baruch Siach's avatar
      arm: mvebu: mcbin: dts: fix PCIe reset polarity · f301ba55
      Baruch Siach authored
      
      The PCIe slot PERST signal is active low. Fix the gpio signal
      description in the dts.
      
      This happened to work because the pcie_dw_mvebu driver sets the reset
      gpio level to 1 (high) to release the reset. The following commit will
      fix that.
      
      Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      f301ba55
    • Michal Simek's avatar
      i2c: mux: Generate longer i2c mux name · c4bd12a7
      Michal Simek authored
      
      For !DM case busses are listed as
      ZynqMP> i2c bus
      Bus 0:	zynq_0
      Bus 1:	zynq_0->PCA9544A@0x75:0
      Bus 2:	zynq_0->PCA9544A@0x75:1
      Bus 3:	zynq_0->PCA9544A@0x75:2
      Bus 4:	zynq_1
      Bus 5:	zynq_1->PCA9548@0x74:0
      Bus 6:	zynq_1->PCA9548@0x74:1
      Bus 7:	zynq_1->PCA9548@0x74:2
      Bus 8:	zynq_1->PCA9548@0x74:3
      Bus 9:	zynq_1->PCA9548@0x74:4
      Bus 10:	zynq_1->PCA9548@0x75:0
      Bus 11:	zynq_1->PCA9548@0x75:1
      Bus 12:	zynq_1->PCA9548@0x75:2
      Bus 13:	zynq_1->PCA9548@0x75:3
      Bus 14:	zynq_1->PCA9548@0x75:4
      Bus 15:	zynq_1->PCA9548@0x75:5
      Bus 16:	zynq_1->PCA9548@0x75:6
      Bus 17:	zynq_1->PCA9548@0x75:7
      
      where is exactly describing i2c bus topology.
      By moving to DM case i2c mux buses are using names from DT and because
      i2c-muxes describing sub busses with the same names like i2c@0, etc it
      is hard to identify which bus is where.
      Linux is adding topology information to i2c-mux busses to identify them
      better.
      This patch is doing the same and composing bus name with topology
      information.
      
      When patch is applied with topology information on zcu102-revA.
      ZynqMP> i2c bus
      Bus 0:	i2c@ff020000
         20: gpio@20, offset len 1, flags 0
         21: gpio@21, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 2:	i2c@ff020000->i2c-mux@75->i2c@0
      Bus 3:	i2c@ff020000->i2c-mux@75->i2c@1
      Bus 4:	i2c@ff020000->i2c-mux@75->i2c@2
      Bus 1:	i2c@ff030000  (active 1)
         74: i2c-mux@74, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 5:	i2c@ff030000->i2c-mux@74->i2c@0  (active 5)
         54: eeprom@54, offset len 1, flags 0
      Bus 6:	i2c@ff030000->i2c-mux@74->i2c@1
      Bus 7:	i2c@ff030000->i2c-mux@74->i2c@2
      Bus 8:	i2c@ff030000->i2c-mux@74->i2c@3
      Bus 9:	i2c@ff030000->i2c-mux@74->i2c@4
      Bus 10:	i2c@ff030000->i2c-mux@75->i2c@0
      Bus 11:	i2c@ff030000->i2c-mux@75->i2c@1
      Bus 12:	i2c@ff030000->i2c-mux@75->i2c@2
      Bus 13:	i2c@ff030000->i2c-mux@75->i2c@3
      Bus 14:	i2c@ff030000->i2c-mux@75->i2c@4
      Bus 15:	i2c@ff030000->i2c-mux@75->i2c@5
      Bus 16:	i2c@ff030000->i2c-mux@75->i2c@6
      Bus 17:	i2c@ff030000->i2c-mux@75->i2c@7
      
      Behavior before the patch is applied.
      ZynqMP> i2c bus
      Bus 0:	i2c@ff020000
         20: gpio@20, offset len 1, flags 0
         21: gpio@21, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 2:	i2c@0
      Bus 3:	i2c@1
      Bus 4:	i2c@2
      Bus 1:	i2c@ff030000  (active 1)
         74: i2c-mux@74, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 5:	i2c@0  (active 5)
         54: eeprom@54, offset len 1, flags 0
      Bus 6:	i2c@1
      Bus 7:	i2c@2
      Bus 8:	i2c@3
      Bus 9:	i2c@4
      Bus 10:	i2c@0
      Bus 11:	i2c@1
      Bus 12:	i2c@2
      Bus 13:	i2c@3
      Bus 14:	i2c@4
      Bus 15:	i2c@5
      Bus 16:	i2c@6
      Bus 17:	i2c@7
      
      Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Reviewed-by: default avatarHeiko Schocher <hs@denx.de>
      c4bd12a7
    • Michal Simek's avatar
      i2c: Fill req_seq in i2c_post_bind() · 61607225
      Michal Simek authored
      
      For i2c controllers which are missing alias in DT there is no req_seq
      setup. This function is setting up proper ID based on highest found
      alias ID.
      
      On zcu102 this is the behavior when patch is applied.
      ZynqMP> i2c bus
      Bus 0:	i2c@ff020000
         20: gpio@20, offset len 1, flags 0
         21: gpio@21, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 2:	i2c@0
      Bus 3:	i2c@1
      Bus 4:	i2c@2
      Bus 1:	i2c@ff030000  (active 1)
         74: i2c-mux@74, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus 5:	i2c@0  (active 5)
         54: eeprom@54, offset len 1, flags 0
      Bus 6:	i2c@1
      Bus 7:	i2c@2
      Bus 8:	i2c@3
      Bus 9:	i2c@4
      Bus 10:	i2c@0
      Bus 11:	i2c@1
      Bus 12:	i2c@2
      Bus 13:	i2c@3
      Bus 14:	i2c@4
      Bus 15:	i2c@5
      Bus 16:	i2c@6
      Bus 17:	i2c@7
      
      Before this patch applied (controllers have -1 ID)
      ZynqMP> i2c bus
      Bus 0:	i2c@ff020000
         20: gpio@20, offset len 1, flags 0
         21: gpio@21, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus -1:	i2c@0
      Bus -1:	i2c@1
      Bus -1:	i2c@2
      Bus 1:	i2c@ff030000  (active 1)
         74: i2c-mux@74, offset len 1, flags 0
         75: i2c-mux@75, offset len 1, flags 0
      Bus -1:	i2c@0  (active 0)
         54: eeprom@54, offset len 1, flags 0
      Bus -1:	i2c@1
      Bus -1:	i2c@2
      Bus -1:	i2c@3
      Bus -1:	i2c@4
      Bus -1:	i2c@0
      Bus -1:	i2c@1
      Bus -1:	i2c@2
      Bus -1:	i2c@3
      Bus -1:	i2c@4
      Bus -1:	i2c@5
      Bus -1:	i2c@6
      Bus -1:	i2c@7
      
      Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      Reviewed-by: default avatarHeiko Schocher <hs@denx.de>
      61607225
    • Michal Simek's avatar
      i2c: dm: Record maximum id of devices before probing devices · 6bfacc8a
      Michal Simek authored
      
      There is a need to find out the first free i2c ID which can be used for
      i2s buses (including i2c buses connected to i2c mux). Do it early in
      init and share this variable with other i2c classes for uniq bus
      identification.
      
      add from hs:
      fix build problem in i2c-uclass.c for omap devices
      
      Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      Reviewed-by: default avatarHeiko Schocher <hs@denx.de>
      6bfacc8a
  3. Feb 10, 2019
  4. Feb 09, 2019
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