- Dec 15, 2019
-
-
Simon Glass authored
At present these options cannot be enabled for SPL/TPL, but this can be useful in some cases. Add Kconfig options to allow it. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
-
Simon Glass authored
Allow this driver to set up an IO address in SPL using an 'early-regs' property. This allows SPL to use the I2C driver without having to enable the full PCI stack. Also split out ofdata_to_platdata in designware driver since this is more correct, and more convenient for the new logic. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
-
Simon Glass authored
Drivers are not allowed to use static data since they may be used in SPL where BSS is not available. It is possible that driver model may provide support for numbering devices in the future. But for now, move this to global_data. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
-
Simon Glass authored
This is hacked into the driver at present. It seems better to have it as a separate driver that uses the base driver. Create a new file and put the X86 code into it. Actually the Baytrail settings should really come from the device tree. Note that 'has_max_speed' is added as well. This is currently always false but since only Baytrail provides the config, it does not affect operation for other devices. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Heiko Schocher <hs@denx.de> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
-
Simon Glass authored
Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
-
Simon Glass authored
At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
-
Simon Glass authored
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
-
- Dec 11, 2019
-
-
Michael Auchter authored
This fixes an issue that would cause I2C writes to timeout when the number of bytes is a multiple of the FIFO depth (i.e. 16 bytes). Within the transfer loop, after writing the data register with a new byte to transfer, if the transfer size equals the FIFO depth, the loop pauses until the INTERRUPT_COMP bit asserts to indicate data has been sent. This same check is performed after the loop as well to ensure data has been transferred prior to returning. In the case where the amount of data to be written is a multiple of the FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to assert after writing the final byte, and then wait for this bit to assert once more. However, since the transfer has finished at this point, no new data has been written to the data register, and hence INTERRUPT_COMP will never assert. Fix this by only waiting for INTERRUPT_COMP in the transfer loop if there's still data to be written. Signed-off-by:
Michael Auchter <michael.auchter@ni.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
-
Michael Auchter authored
Chromium EC commands can be up to 16-bits, so using a uint8_t here can cause truncation. Update to use a uint instead. It looks like this should likely have been done as a part of 9fea76f5, but this function was skipped for some reason. Signed-off-by:
Michael Auchter <michael.auchter@ni.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by:
Simon Glass <sjg@chromium.org>
-
- Dec 10, 2019
-
-
Heinrich Schuchardt authored
Due to a conversion error the sandbox does not accept byte values 0x80-0xff from the keyboard. The UEFI extended text input unit test requires Unicode support. Use unsigned char for the serial buffer. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com>
-
Rick Chen authored
When ax25-ae350 try to enable v5l2 cache driver in SPL configuration, it need this option for cache support in SPL. Signed-off-by:
Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
-
- Dec 09, 2019
-
-
Vignesh Raghavendra authored
Add new compatible to handle J721e SoC Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Grygorii Strashko <grygorii.strashko@ti.com>
-
Vignesh Raghavendra authored
Get flow ID information for RX DMA channel using dma_get_cfg() interface instead of reading from DT. This is required in order to avoid DT update whenever there is change in the range of flow ID allocated to the host. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Grygorii Strashko <grygorii.strashko@ti.com>
-
Vignesh Raghavendra authored
Implement dma_get_cfg() interface to pass flow id information for DMA clients to use. This is needed because on K3 SoCs, CPSW (ethernet) and UDMA (DMA provider) support "flows" within a given RX DMA channel. This allows different network packets to be segregated while using same RX DMA channel. In order for basic ethernet to work, CPSW slave must be aware of the flow ID allocated for the RX channel by the DMA driver. This interface allows CPSW to query flow ID from DMA provider and configure it in CPSW HW. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Grygorii Strashko <grygorii.strashko@ti.com>
-
Vignesh Raghavendra authored
Sometimes, there would be a need to exchange data between DMA provider and DMA client which are very specific to DMA driver of the SoC/platform and are not generic enough to be put into struct dma. Therefore, introduce dma_get_cfg() interface to get DMA provider specific data from client device. Clients can use unique configuration ID flags to get different configuration data from DMA driver. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Grygorii Strashko <grygorii.strashko@ti.com>
-
Cédric Le Goater authored
Fixes: e7668497 ("net: ftgmac100: convert the RX/TX descriptor arrays") Signed-off-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Joel Stanley <joel@jms.id.au> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
This bus is used to access internal SoC PHYs. These PHYs are configured by the ENETC driver directly, but it's useful to have command line access to this MDIO to debug the system especially when using new external PHYs. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
On some boards MDIO may get stuck if it detects echo on the line. This is a know hardware issue, there is a board fix for it. In case we're running on a board that doesn't have the fix, we don't want to loop here forever and freeze U-Boot. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
This reduces the time needed to establish a link as we don't reset the link each time the interface is used. Our Link capabilities do not change at run-time so there is no need to re-apply PHY configuration each time. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
The original code enabled link speeds up to 1Gbps, but the interface can go up to 2.5G, enable that speed to in PHY AN mask. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
Uses the new dm_eth_phy_connect helper to connect to the PHY to simplify the code. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
Apply 10G PCS init for USXGMII, XFI interface types. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
In some cases the link on the system interface of the aquantia PHY comes up after the link on line interface. The link state loop only checks the line side, which may result in first packet sent being lost. Use aquantia_link_is_up instead, which checks both system and line side on gen 2/3 PHYs to avoid losing the 1st packet. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses on this interface are normally set up by PHY firmware, but depending on the board they may end up not being unique. Add an optional DT property used to change SMBus address if needed. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
MDI pins up to the RJ45 connector may be reversed on the board and the default PHY configuration applied by firmware may or may not match that. Add an optional DT property to configure MDI reversal for this case. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
If PHY is not ready for data by the time _config is called, reconfigure the PHY system interface to use the proper protocol based on phydev->interface, just in case the defaults set by PHY firmware don't match current configuration. Signed-off-by:
Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
Uses the data field in phy_driver structure to identify the PHY generation. This is useful for custom configuration as non-generic PHY registers are not 100% compatible between generations. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Alex Marginean authored
The PHY supports XFI and USXGMII, the notable difference being that USX AN is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and detects whether USX AN should be enabled or not using a PHY status register. Keep that functionality too, so we don't break existing drivers. Signed-off-by:
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Anatolij Gustschin authored
Fix vendor name in MV88E61xx option description. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Reviewed-by:
Chris Packham <judge.packham@gmail.com> Tested-by:
Chris Packham <judge.packham@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Anatolij Gustschin authored
Support probing and init for 88E6071 switch. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Reviewed-by:
Chris Packham <judge.packham@gmail.com> Tested-by:
Chris Packham <judge.packham@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Anatolij Gustschin authored
On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Reviewed-by:
Chris Packham <judge.packham@gmail.com> Tested-by:
Chris Packham <judge.packham@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Anatolij Gustschin authored
On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Reviewed-by:
Chris Packham <judge.packham@gmail.com> Tested-by:
Chris Packham <judge.packham@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Anatolij Gustschin authored
Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Nicolas Ferre authored
The KSZ8081 PHY has a factory test mode which is set at the de-assertion of the reset line based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a pull-up, the factory test mode should be cleared by manually writing a 0 (according to the datasheet). Create another ksz8081_config function to handle this case. Suggested-by:
Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Florin Chiculita authored
Aquantia quad-phys may take longer to initialize. This commit adds a polling mechanism for a global alarm bit that tells if phy init sequence is completed. Signed-off-by:
Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Josef Holzmayr authored
This allows passing arbitrary addresses through macb_miiphy_read and macb_miiphy_write, therefore enabling the mii command to access all mdio bus devices instead of only the defined phy. Signed-off-by:
Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Josef Holzmayr authored
To support accessing arbitrary addresses the mii/mdio bus it is necessary that the macb_mdio_read and macb_mdio_write functions do not implicitly use the address of the connected phy. The function signature is extended according to the Linux kernel equivalent. Signed-off-by:
Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Stefan Roese authored
I've noticed that in most cases when genphy_update_link() is called, the ethernet driver (mt7628-eth in this case) fails with the first ethernet packets. Resulting in a timeout of the first tftp command. Increasing the delay in the link check look from 1 to 50 ms and moving it below the BMSR register read fixes this issue, resulting in a stable ethernet traffic, even after initial link autonogotiation. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Weijie Gao <weijie.gao@mediatek.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Thierry Reding authored
This version of the RTL-8168 chip can be found on some add-in cards sold by CSL-Computer GmbH & Co. KG. The chip isn't special in any way, but it needs to have the ChipCmd register programmed after the DMA descriptors have been set up, so make sure that happens by adding an entry to the chip information table. Signed-off-by:
Thierry Reding <treding@nvidia.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Nevo Hed authored
Changes to mvpp2.c require the MVMDIO module which in turn uses DM_MDIO. Signed-off-by:
Nevo Hed <nhed+github@starry.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-