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  1. Nov 09, 2013
    • Paul Burton's avatar
      malta: enable CONFIG_PCNET_79C973, PCNET_HAS_PROM, CONFIG_CMD_DHCP · e0878af8
      Paul Burton authored
      
      This model of the pcnet is used in current Malta boards, at least in the
      Malta-R rev 3. Enable support for it.
      
      The Malta also has the ethernet controller PROM containing its MAC
      address, so enable support for that in order to read that MAC address.
      
      DHCP is a very useful feature to have available for many networks,
      enable support for it also.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      e0878af8
    • Paul Burton's avatar
      malta: display "U-boot" on the LCD screen · e0ada631
      Paul Burton authored
      
      Displaying a message on the LCD screen is a simple yet effective way to
      show the user that the board has booted successfully.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      e0ada631
    • Paul Burton's avatar
      malta: support for coreFPGA6 boards · baf37f06
      Paul Burton authored
      
      This patch adds support for running on Malta boards using coreFPGA6
      core cards, including support for the msc01 system controller used
      with them. The system controller is detected at runtime allowing one
      U-boot binary to run on a Malta with either.
      
      Due to the PCI I/O base differing between Maltas using gt64120 & msc01
      system controllers, the UART setup is modified slightly. A second UART
      is added so that there is one pointing at the correct address for each
      system controller. The Malta board then defines its own
      default_serial_console function to select the correct one at runtime.
      The incorrect UART will simply not function.
      
      Tested on:
        - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
          with and without an L2 cache.
        - QEMU.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      baf37f06
    • Paul Burton's avatar
      malta: setup super I/O UARTs · a257f626
      Paul Burton authored
      
      On a real Malta the Super I/O needs to be configured before we are able
      to access the UARTs. This patch performs that configuration, setting up
      the UARTs in the same way that YAMON would.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      a257f626
    • Paul Burton's avatar
      qemu-malta: rename to just "malta" · 7a9d109b
      Paul Burton authored
      
      This is in preparation for adapting this board to function correctly on
      a physical MIPS Malta board. The board is moved into an "imgtec" vendor
      directory at the same time in order to ready us for any other boards
      supported by Imagination in the future.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      7a9d109b
    • Paul Burton's avatar
      pci.h: allow inclusion in assembly source · fa5cec03
      Paul Burton authored
      
      This patch simply #ifdef's out the C-specific parts of pci.h when it is
      included by an assembly file. This will allow the macros it contains to
      be used from assembly source as will be done in a followup commit adding
      support for more modern MIPS Malta boards.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      fa5cec03
    • Paul Burton's avatar
      pcnet: enable the NOUFLO feature · 62715a2c
      Paul Burton authored
      
      On relatively slow boards (such as the MIPS Malta with an FPGA core
      card) it can be extremely common for transmits to underflow - to the
      point where it appears they simply do not work at all. Setting the
      NOUFLO bit causes the ethernet controller to not begin transmission on
      the wire until a transmit start point is reached. Setting that transmit
      start point to the full packet will cause the controller to only
      transmit the packet once it has buffered it entirely thus preventing any
      transmit underflows from occuring and allowing the controller to
      function on slower boards.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      62715a2c
    • Paul Burton's avatar
      pcnet: add cache flushing & invalidation · f3ac866c
      Paul Burton authored
      
      Ensure that the view of memory from the CPU & the ethernet controller is
      coherent at the various points where they exchange data. This prevents
      stale data from being transmitted or received, and prevents the driver
      from getting stuck waiting for the ethernet controller to update
      descriptors when in reality it has but the old values are being read
      from cache.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      f3ac866c
    • Paul Burton's avatar
      pcnet: s/le16_to_cpu/cpu_to_le16/ in pcnet_send · a9540041
      Paul Burton authored
      
      This should cause no change to the generated code, but is semantically
      correct.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      a9540041
    • Paul Burton's avatar
      pcnet: code style cleanup · 6011dabd
      Paul Burton authored
      
      Fix up the code to match Documentation/CodingStyle. This is mostly
      removing extraneous spaces.
      
      No functional change is intended.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      6011dabd
    • Paul Burton's avatar
      mips32: detect L1 cache sizes if they're not defined · fa476f75
      Paul Burton authored
      
      For boards such as the MIPS Malta with an FPGA core card it is desirable
      to be able to detect the L1 cache sizes at runtime, since they are not
      dependant upon the board but on the FPGA bitstream in use. This patch
      performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are
      not defined by the board configuration. In cases where the sizes are
      detected this patch also removes the restriction that the I-cache &
      D-cache line sizes must be the same, as this is not necessarily true.
      
      If the cache sizes are defined by a configuration then they will be
      hardcoded as before, so this patch will not add overhead to such
      boards.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      fa476f75
  2. Nov 08, 2013
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